{"id":"https://openalex.org/W2169287990","doi":"https://doi.org/10.1109/iccd.2003.1240902","title":"Design of resonant global clock distributions","display_name":"Design of resonant global clock distributions","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W2169287990","doi":"https://doi.org/10.1109/iccd.2003.1240902","mag":"2169287990"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2003.1240902","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240902","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068763689","display_name":"S.C. Chan","orcid":null},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.C. Chan","raw_affiliation_strings":["Department of Electrical Engineering, Columbia University, New York, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Columbia University, New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002706979","display_name":"Kenneth L. Shepard","orcid":"https://orcid.org/0000-0003-0665-6775"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K.L. Shepard","raw_affiliation_strings":["Department of Electrical Engineering, Columbia University, New York, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Columbia University, New York, NY, USA","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054155143","display_name":"P.J. Restle","orcid":"https://orcid.org/0000-0002-3124-4265"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P.J. Restle","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":58,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"248","last_page":"253"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7667275071144104},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6376607418060303},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5872014760971069},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5751143097877502},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5601403117179871},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5399596095085144},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5369465351104736},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5259064435958862},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5108146667480469},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5024561882019043},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4937816560268402},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.47310638427734375},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4712900221347809},{"id":"https://openalex.org/keywords/inductor","display_name":"Inductor","score":0.4519559442996979},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.44126033782958984},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42691951990127563},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.41185638308525085},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.36242207884788513},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3170773983001709},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2956885099411011},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.260938823223114},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.22021684050559998},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15958452224731445},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12496483325958252}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7667275071144104},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6376607418060303},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5872014760971069},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5751143097877502},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5601403117179871},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5399596095085144},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5369465351104736},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5259064435958862},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5108146667480469},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5024561882019043},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4937816560268402},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.47310638427734375},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4712900221347809},{"id":"https://openalex.org/C144534570","wikidata":"https://www.wikidata.org/wiki/Q5325","display_name":"Inductor","level":3,"score":0.4519559442996979},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.44126033782958984},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42691951990127563},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.41185638308525085},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.36242207884788513},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3170773983001709},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2956885099411011},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.260938823223114},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.22021684050559998},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15958452224731445},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12496483325958252},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2003.1240902","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240902","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1497390434","https://openalex.org/W1506631106","https://openalex.org/W2115468286","https://openalex.org/W2119512278","https://openalex.org/W2122724421","https://openalex.org/W2128060653","https://openalex.org/W2131239505","https://openalex.org/W2131894786","https://openalex.org/W2153448889","https://openalex.org/W2167004581","https://openalex.org/W2170191597","https://openalex.org/W2788994432","https://openalex.org/W4233923396","https://openalex.org/W6677917395","https://openalex.org/W6815584514"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2474747038","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W2169618112","https://openalex.org/W2496244846","https://openalex.org/W3013924136","https://openalex.org/W2587665273"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2,62],"new":[3],"approach":[4],"to":[5,19,58,99],"global":[6],"clock":[7,22,30,50],"distribution":[8],"in":[9],"which":[10],"traditional":[11],"tree-driven":[12],"grids":[13],"are":[14,97],"augmented":[15],"with":[16],"on-chip":[17],"inductors":[18],"resonate":[20],"the":[21,25,29,38,41,55,73,76,85,89,101],"capacitance":[23,87],"at":[24],"fundamental":[26,42],"frequency":[27],"of":[28,40,66,75,88,110],"node.":[31],"Rather":[32],"than":[33],"being":[34],"dissipated":[35],"as":[36],"heat,":[37],"energy":[39,56],"resonates":[43],"between":[44],"electric":[45],"and":[46,93,104],"magnetic":[47],"forms.":[48],"The":[49],"drivers":[51],"must":[52],"only":[53],"provide":[54],"necessary":[57,98],"overcome":[59],"losses.":[60],"As":[61],"result,":[63],"power":[64],"reduction":[65],"over":[67],"80%":[68],"is":[69,81,91],"possible":[70],"depending":[71],"on":[72],"Q":[74],"resonant":[77],"system.":[78],"Clock":[79],"latency":[80],"also":[82],"improved":[83],"because":[84,109],"effective":[86],"grid":[90],"lower,":[92],"fewer":[94],"buffer":[95,113],"stages":[96],"drive":[100],"grid.":[102],"Skew":[103],"jitter":[105],"reductions":[106],"come":[107],"about":[108],"this":[111],"reduced":[112],"latency.":[114]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":6}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
