{"id":"https://openalex.org/W2114121007","doi":"https://doi.org/10.1109/iccd.2002.1106790","title":"Power analysis of bipartition and dual-encoding architecture for pipelined circuits","display_name":"Power analysis of bipartition and dual-encoding architecture for pipelined circuits","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2114121007","doi":"https://doi.org/10.1109/iccd.2002.1106790","mag":"2114121007"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2002.1106790","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106790","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026137532","display_name":"Shanq-Jang Ruan","orcid":"https://orcid.org/0000-0003-1075-8512"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shanq-Jang Ruan","raw_affiliation_strings":["Department of EE, National Taiwan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of EE, National Taiwan University, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008269844","display_name":"Chia-Lin Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I200332995","display_name":"TU Dortmund University","ror":"https://ror.org/01k97gp34","country_code":"DE","type":"education","lineage":["https://openalex.org/I200332995"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Chia-Lin Ho","raw_affiliation_strings":["Computer Engineering Institute, University of Dortmund, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Institute, University of Dortmund, Germany","institution_ids":["https://openalex.org/I200332995"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064183605","display_name":"Edwin Naroska","orcid":"https://orcid.org/0009-0004-8742-4566"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"E. Naroska","raw_affiliation_strings":["Department of CSIE, National Taiwan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Taiwan University, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017526842","display_name":"Feipei Lai","orcid":"https://orcid.org/0000-0001-7147-8122"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Feipei Lai","raw_affiliation_strings":["Department of CSIE & Department of EE, National Taiwan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of CSIE & Department of EE, National Taiwan University, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.25453456,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"146","issue":null,"first_page":"327","last_page":"332"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7953470945358276},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7918699979782104},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.6744251847267151},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5851775407791138},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5551022291183472},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5437362194061279},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.4861688017845154},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4790179133415222},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.47434723377227783},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47064274549484253},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4696119427680969},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4173475503921509},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4081673324108124},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.334297776222229},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33195140957832336},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10132208466529846},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07759055495262146},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07415595650672913}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7953470945358276},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7918699979782104},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.6744251847267151},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5851775407791138},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5551022291183472},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5437362194061279},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.4861688017845154},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4790179133415222},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.47434723377227783},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47064274549484253},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4696119427680969},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4173475503921509},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4081673324108124},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.334297776222229},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33195140957832336},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10132208466529846},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07759055495262146},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07415595650672913},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccd.2002.1106790","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106790","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},{"id":"pmh:oai:140.112.114.62:246246/2007041910021065","is_oa":false,"landing_page_url":"http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021065","pdf_url":null,"source":{"id":"https://openalex.org/S4306402491","display_name":"NTUR (\u81fa\u7063\u6a5f\u69cb\u5178\u85cf)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I16733864","host_organization_name":"National Taiwan University","host_organization_lineage":["https://openalex.org/I16733864"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8899999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1588764976","https://openalex.org/W1950155314","https://openalex.org/W1994298038","https://openalex.org/W2066179021","https://openalex.org/W2106157873","https://openalex.org/W2110615063","https://openalex.org/W2111485030","https://openalex.org/W2115283580","https://openalex.org/W2142612120","https://openalex.org/W2169613818","https://openalex.org/W2170463050","https://openalex.org/W2567389468","https://openalex.org/W2615428366","https://openalex.org/W6640906542","https://openalex.org/W6681385422","https://openalex.org/W6684936905"],"related_works":["https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W2163776294","https://openalex.org/W3141297747","https://openalex.org/W4248668797","https://openalex.org/W2111485030","https://openalex.org/W818963952","https://openalex.org/W1939541994","https://openalex.org/W1851795671","https://openalex.org/W2146663621"],"abstract_inverted_index":{"In":[0,101],"this":[1,49],"paper":[2],"we":[3,69],"propose":[4,70],"a":[5,27,38,71,78],"bipartition":[6,97],"dual-encoding":[7],"architecture":[8],"for":[9,73,110,115],"low":[10],"power":[11,31,75,104],"pipelined":[12,47,79,111,118],"circuit.":[13],"Pipelined":[14],"circuits":[15],"consist":[16],"of":[17,30,45,56,77],"combinational":[18,84],"logic":[19,85],"blocks":[20,86],"separated":[21],"by":[22,53,108],"registers":[23,58,82,95,112],"which":[24],"usually":[25],"consume":[26],"large":[28],"amount":[29],"Although":[32],"the":[33,46,54,57,60,88,94,116],"clock":[34],"gated":[35],"technique":[36,72],"is":[37,51],"promising":[39],"approach":[40,50,92],"to":[41],"reduce":[42],"switching":[43],"activities":[44],"registers,":[48],"restricted":[52],"placement":[55],"and":[59,83,98,113],"additional":[61],"control":[62],"signals":[63],"that":[64],"must":[65],"be":[66],"generated.":[67],"Thus,":[68],"optimizing":[74],"dissipation":[76],"circuit":[80],"addressing":[81],"at":[87],"same":[89],"time.":[90],"Our":[91],"modifies":[93],"using":[96],"encoding":[99],"techniques.":[100],"our":[102],"experiments":[103],"consumption":[105],"were":[106],"reduced":[107],"72.9%":[109],"30.4%":[114],"total":[117],"stage":[119],"on":[120],"average.":[121]},"counts_by_year":[],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}
