{"id":"https://openalex.org/W2099543523","doi":"https://doi.org/10.1109/iccd.2002.1106778","title":"Performance enhancements to the Active Memory System","display_name":"Performance enhancements to the Active Memory System","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2099543523","doi":"https://doi.org/10.1109/iccd.2002.1106778","mag":"2099543523"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2002.1106778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038574274","display_name":"Witawas Srisa\u2010an","orcid":"https://orcid.org/0000-0003-0021-5696"},"institutions":[{"id":"https://openalex.org/I114395901","display_name":"University of Nebraska\u2013Lincoln","ror":"https://ror.org/043mer456","country_code":"US","type":"education","lineage":["https://openalex.org/I114395901"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Witawas Srisa-an","raw_affiliation_strings":["Computer Science and Engineering, University of Nebraska, Lincolnshire, NE, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, University of Nebraska, Lincolnshire, NE, USA","institution_ids":["https://openalex.org/I114395901"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108622100","display_name":"C.-T.D. Lo","orcid":null},"institutions":[{"id":"https://openalex.org/I45438204","display_name":"The University of Texas at San Antonio","ror":"https://ror.org/01kd65564","country_code":"US","type":"education","lineage":["https://openalex.org/I45438204"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.-T.D. Lo","raw_affiliation_strings":["Department of Computer Science, University of Texas, San Antonio, San Antonio, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Texas, San Antonio, San Antonio, TX, USA","institution_ids":["https://openalex.org/I45438204"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055158787","display_name":"J. Morris Chang","orcid":"https://orcid.org/0000-0002-0660-7191"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.M. Chang","raw_affiliation_strings":["Electrical and Computer Engineering, Iowa State University, Ames, IA, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Iowa State University, Ames, IA, USA","institution_ids":["https://openalex.org/I173911158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5038574274"],"corresponding_institution_ids":["https://openalex.org/I114395901"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.14651729,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":null,"first_page":"249","last_page":"256"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/garbage-collection","display_name":"Garbage collection","score":0.8121659159660339},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7865278720855713},{"id":"https://openalex.org/keywords/garbage","display_name":"Garbage","score":0.6921032667160034},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5546149015426636},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5152111649513245},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4906686544418335},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47213083505630493},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.46060994267463684},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42373138666152954},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.20336416363716125}],"concepts":[{"id":"https://openalex.org/C105122174","wikidata":"https://www.wikidata.org/wiki/Q322202","display_name":"Garbage collection","level":3,"score":0.8121659159660339},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7865278720855713},{"id":"https://openalex.org/C75403996","wikidata":"https://www.wikidata.org/wiki/Q5521979","display_name":"Garbage","level":2,"score":0.6921032667160034},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5546149015426636},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5152111649513245},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4906686544418335},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47213083505630493},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.46060994267463684},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42373138666152954},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.20336416363716125},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2002.1106778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1560113744","https://openalex.org/W1583464938","https://openalex.org/W1899349177","https://openalex.org/W1968887845","https://openalex.org/W1992695751","https://openalex.org/W2071455557","https://openalex.org/W2113486106","https://openalex.org/W2118420116","https://openalex.org/W2121762814","https://openalex.org/W2136764572","https://openalex.org/W2141001602","https://openalex.org/W2162364282","https://openalex.org/W3198160809","https://openalex.org/W4236739790","https://openalex.org/W4301715052","https://openalex.org/W6639498907","https://openalex.org/W6680298290"],"related_works":["https://openalex.org/W2132258996","https://openalex.org/W2245694847","https://openalex.org/W4387773637","https://openalex.org/W4381304378","https://openalex.org/W2188602196","https://openalex.org/W3174776489","https://openalex.org/W1700460898","https://openalex.org/W4297378365","https://openalex.org/W2808342711","https://openalex.org/W2785868435"],"abstract_inverted_index":{"The":[0,26,53,107,125],"Active":[1,34],"Memory":[2,35],"System":[3],"-":[4,10],"a":[5,14,40,45,93],"garbage":[6,21,51,90,120],"collected":[7],"memory":[8],"module":[9],"was":[11,32],"introduced":[12,98],"as":[13,132,134,145,147],"way":[15],"to":[16,48,71,88,99],"provide":[17],"hardware":[18,102,141],"support":[19],"for":[20,59],"collection":[22,121],"in":[23,29,127],"embedded":[24],"systems.":[25],"major":[27],"component":[28],"the":[30,33,72,86,101,105,112,117,137,140],"design":[31,54,73],"Processor":[36],"(AMP)":[37],"that":[38,77,84,111],"utilized":[39],"set":[41],"of":[42,74,104,119,154],"bit-maps":[43],"and":[44,62,151],"combinational":[46],"circuit":[47],"perform":[49,80,89],"mark-sweep":[50],"collection.":[52,91],"can":[55,79,115,130,143],"achieve":[56],"constant":[57],"time":[58,129],"both":[60],"allocation":[61],"sweeping.":[63],"In":[64],"this":[65],"paper":[66],"two":[67],"enhancements":[68],"are":[69],"made":[70],"AMP":[75],"so":[76],"it":[78],"one-bit":[81],"reference":[82],"counting":[83],"postpones":[85],"need":[87],"Moreover,":[92],"caching":[94,138],"mechanism":[95],"is":[96],"also":[97],"reduce":[100,116],"cost":[103,142],"design.":[106],"experimental":[108],"results":[109],"show":[110],"proposed":[113],"modification":[114],"number":[118],"invocations":[122],"by":[123],"76%.":[124],"speed-up":[126],"marking":[128],"be":[131,144],"much":[133],"5.81.":[135],"With":[136],"mechanism,":[139],"small":[146],"27":[148],"K":[149],"gates":[150],"6":[152],"KB":[153],"SRAM.":[155]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}