{"id":"https://openalex.org/W2153455372","doi":"https://doi.org/10.1109/iccd.2002.1106770","title":"An extended class of sequential circuits with combinational test generation complexity","display_name":"An extended class of sequential circuits with combinational test generation complexity","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2153455372","doi":"https://doi.org/10.1109/iccd.2002.1106770","mag":"2153455372"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2002.1106770","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106770","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070572924","display_name":"Michiko Inoue","orcid":"https://orcid.org/0000-0002-9837-5147"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"M. Inoue","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Japan","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081694573","display_name":"C. Jinno","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"C. Jinno","raw_affiliation_strings":["Mitsubishi Electric Corporation Limited, Japan"],"affiliations":[{"raw_affiliation_string":"Mitsubishi Electric Corporation Limited, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111955990","display_name":"Hideo Fujiwara","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Fujiwara","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Japan","institution_ids":["https://openalex.org/I75917431"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5070572924"],"corresponding_institution_ids":["https://openalex.org/I75917431"],"apc_list":null,"apc_paid":null,"fwci":0.7546,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.74291281,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"200","last_page":"205"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.853714108467102},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6359195709228516},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6295355558395386},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6187471151351929},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.5640726685523987},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5346205830574036},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5306564569473267},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42303013801574707},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.36987394094467163},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11731332540512085},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07570615410804749}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.853714108467102},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6359195709228516},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6295355558395386},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6187471151351929},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.5640726685523987},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5346205830574036},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5306564569473267},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42303013801574707},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.36987394094467163},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11731332540512085},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07570615410804749},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2002.1106770","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106770","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1483338234","https://openalex.org/W1498116972","https://openalex.org/W1554885925","https://openalex.org/W1988380797","https://openalex.org/W2001642815","https://openalex.org/W2111667834","https://openalex.org/W2120257283","https://openalex.org/W2132547051","https://openalex.org/W2132684947","https://openalex.org/W2134921041","https://openalex.org/W2160162958","https://openalex.org/W2167747841","https://openalex.org/W4302084786","https://openalex.org/W4302458519","https://openalex.org/W6677995269","https://openalex.org/W6684563726"],"related_works":["https://openalex.org/W1412895167","https://openalex.org/W2132684947","https://openalex.org/W4238986168","https://openalex.org/W2165817266","https://openalex.org/W1493811107","https://openalex.org/W2120257283","https://openalex.org/W2117563988","https://openalex.org/W2161696808","https://openalex.org/W4240466429","https://openalex.org/W2132547051"],"abstract_inverted_index":{"We":[0],"introduce":[1],"a":[2],"class":[3,23],"of":[4,61],"sequential":[5],"circuits":[6,68],"with":[7,16,29,69],"internally":[8,70],"switched":[9,71],"balanced":[10,72],"structure":[11],"which":[12],"allows":[13],"test":[14,18,64],"generation":[15,19,65],"combinational":[17,63],"complexity.":[20],"The":[21],"proposed":[22],"includes":[24],"any":[25,46],"other":[26],"known":[27],"classes":[28],"this":[30],"feature.":[31],"This":[32],"paper":[33],"also":[34],"considers":[35],"faults":[36,52],"in":[37,53],"hold":[38],"registers":[39],"and":[40],"switches":[41],"regarded":[42],"as":[43],"macros,":[44],"while":[45],"related":[47],"work":[48],"does":[49],"not":[50],"consider":[51],"such":[54],"macros.":[55],"Experimental":[56],"results":[57],"show":[58],"the":[59,67],"effectiveness":[60],"using":[62],"for":[66],"structure.":[73]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}