{"id":"https://openalex.org/W2147662327","doi":"https://doi.org/10.1109/iccd.2002.1106761","title":"Adaptive balanced computing (ABC) microprocessor using reconfigurable functional caches (RFCs)","display_name":"Adaptive balanced computing (ABC) microprocessor using reconfigurable functional caches (RFCs)","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2147662327","doi":"https://doi.org/10.1109/iccd.2002.1106761","mag":"2147662327"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2002.1106761","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100441149","display_name":"Hyunsoo Kim","orcid":"https://orcid.org/0000-0002-9892-1080"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"H. Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Iowa State University, Ames, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Iowa State University, Ames, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087267932","display_name":"Arun K. Somani","orcid":"https://orcid.org/0000-0002-6248-4376"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A.K. Somani","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Iowa State University, Ames, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Iowa State University, Ames, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102977539","display_name":"Akhilesh Tyagi","orcid":"https://orcid.org/0000-0002-2101-3594"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Tyagi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Iowa State University, Ames, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Iowa State University, Ames, USA","institution_ids":["https://openalex.org/I173911158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100441149"],"corresponding_institution_ids":["https://openalex.org/I173911158"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21919143,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"138","last_page":"144"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8641115427017212},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7060995697975159},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6123454570770264},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5320711135864258},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5099495649337769},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.49573764204978943},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.48087385296821594},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.479299932718277},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.46890297532081604},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45283010601997375},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.43470245599746704},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.42527303099632263},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4208815395832062},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2217540144920349}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8641115427017212},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7060995697975159},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6123454570770264},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5320711135864258},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5099495649337769},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.49573764204978943},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.48087385296821594},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.479299932718277},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.46890297532081604},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45283010601997375},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.43470245599746704},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.42527303099632263},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4208815395832062},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2217540144920349}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2002.1106761","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2002.1106761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1599366940","https://openalex.org/W1608508249","https://openalex.org/W1969489929","https://openalex.org/W2015284894","https://openalex.org/W2103664057","https://openalex.org/W2117285153","https://openalex.org/W2142033140","https://openalex.org/W2142490124","https://openalex.org/W2147999063","https://openalex.org/W2148911285","https://openalex.org/W2162910994","https://openalex.org/W2165099691","https://openalex.org/W2168244800","https://openalex.org/W2415789591","https://openalex.org/W4237433798","https://openalex.org/W6636579028","https://openalex.org/W6654400801","https://openalex.org/W6677504465","https://openalex.org/W6681750508","https://openalex.org/W6682223283"],"related_works":["https://openalex.org/W2167303720","https://openalex.org/W2086718556","https://openalex.org/W2012518269","https://openalex.org/W2399041033","https://openalex.org/W2072955902","https://openalex.org/W1576527819","https://openalex.org/W4247823503","https://openalex.org/W2046128376","https://openalex.org/W2146079099","https://openalex.org/W2109715593"],"abstract_inverted_index":{"A":[0],"general-purpose":[1,14],"computing":[2,33,37,73],"processor":[3],"performs":[4,57],"a":[5,47,58,71,76,86,100],"wide":[6],"range":[7],"of":[8,13,44,62,79,88,120],"functions.":[9],"Although":[10],"the":[11,36,42,68,89,108,118,132,150],"performance":[12,49],"processors":[15],"has":[16],"been":[17],"steadily":[18],"increasing,":[19],"certain":[20],"software":[21],"technologies":[22],"like":[23],"multimedia":[24,126],"and":[25,82,127,144],"digital":[26],"signal":[27],"processing":[28],"applications":[29,129,143],"demand":[30],"ever":[31],"more":[32],"power.":[34],"If":[35],"resources":[38],"are":[39],"variable":[40],"to":[41,95,116,139,147],"needs":[43],"an":[45],"application,":[46],"better":[48],"can":[50,92],"be":[51,93],"achieved.":[52],"Adaptive":[53],"Balanced":[54],"Computing":[55],"(ABC)":[56],"dynamic":[59],"resource":[60,121,133],"configuration":[61,134],"on-chip":[63],"cache":[64,69,90,114],"memory":[65,91],"by":[66],"converting":[67],"into":[70],"specialized":[72,97],"unit.":[74],"With":[75],"small":[77],"amount":[78],"additional":[80],"logic":[81],"slightly":[83],"modified":[84],"microarchitecture,":[85],"part":[87],"configured":[94],"perform":[96],"computations":[98],"in":[99,112,141,149],"conventional":[101],"processor.":[102],"In":[103],"this":[104],"paper,":[105],"we":[106],"evaluate":[107],"ABC":[109],"using":[110],"RFCs":[111],"various":[113],"organizations":[115],"see":[117],"impact":[119],"reconfiguration.":[122],"The":[123],"simulations":[124],"with":[125],"DSP":[128],"show":[130],"that":[131],"speedups":[135],"ranging":[136],"from":[137,145],"1.04X":[138],"3.94X":[140],"overall":[142],"2.61X":[146],"27.4X":[148],"core":[151],"computations.":[152]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}