{"id":"https://openalex.org/W2119463768","doi":"https://doi.org/10.1109/iccd.2000.878322","title":"Formal verification of an industrial system-on-a-chip","display_name":"Formal verification of an industrial system-on-a-chip","publication_year":2002,"publication_date":"2002-11-08","ids":{"openalex":"https://openalex.org/W2119463768","doi":"https://doi.org/10.1109/iccd.2000.878322","mag":"2119463768"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2000.878322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2000.878322","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 2000 International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050061015","display_name":"Hoon Choi","orcid":"https://orcid.org/0000-0002-4435-3997"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Hoon Choi","raw_affiliation_strings":["SOC Development, System LSI, Samsung Electronics Company Limited, South Korea"],"affiliations":[{"raw_affiliation_string":"SOC Development, System LSI, Samsung Electronics Company Limited, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084533010","display_name":"Myung-Kyoon Yim","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Myung-Kyoon Yim","raw_affiliation_strings":["SOC Development, System LSI, Samsung Electronics Company Limited, South Korea"],"affiliations":[{"raw_affiliation_string":"SOC Development, System LSI, Samsung Electronics Company Limited, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100334523","display_name":"Jae-Young Lee","orcid":"https://orcid.org/0000-0001-8023-0081"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jae-Young Lee","raw_affiliation_strings":["SOC Development, System LSI, Samsung Electronics Company Limited, South Korea"],"affiliations":[{"raw_affiliation_string":"SOC Development, System LSI, Samsung Electronics Company Limited, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003585361","display_name":"Byeong-Whee Yun","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Byeong-Whee Yun","raw_affiliation_strings":["SOC Development, System LSI, Samsung Electronics Company Limited, South Korea"],"affiliations":[{"raw_affiliation_string":"SOC Development, System LSI, Samsung Electronics Company Limited, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066971192","display_name":"Yun-Tae Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yun-Tae Lee","raw_affiliation_strings":["SOC Development, System LSI, Samsung Electronics Company Limited, South Korea"],"affiliations":[{"raw_affiliation_string":"SOC Development, System LSI, Samsung Electronics Company Limited, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5050061015"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":1.0163,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.75956445,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"453","last_page":"458"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11450","display_name":"Model-Driven Software Engineering Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8116339445114136},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.7823950052261353},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.7632823586463928},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.7060111165046692},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6815564632415771},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.6348853707313538},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.569656491279602},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.5374821424484253},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime verification","score":0.5253526568412781},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.48539623618125916},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4736707806587219},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.43531325459480286},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.4213769733905792},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37472501397132874},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32333630323410034},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15631240606307983}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8116339445114136},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.7823950052261353},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.7632823586463928},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.7060111165046692},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6815564632415771},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6348853707313538},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.569656491279602},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.5374821424484253},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.5253526568412781},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.48539623618125916},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4736707806587219},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.43531325459480286},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.4213769733905792},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37472501397132874},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32333630323410034},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15631240606307983},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2000.878322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2000.878322","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 2000 International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1921633840","https://openalex.org/W2069984295","https://openalex.org/W2103054929","https://openalex.org/W2122464403","https://openalex.org/W2151415035","https://openalex.org/W2161320179","https://openalex.org/W2532815277"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2106507440","https://openalex.org/W3023586562","https://openalex.org/W3120172095","https://openalex.org/W2162615969","https://openalex.org/W1496505755","https://openalex.org/W4375857205","https://openalex.org/W2105593427","https://openalex.org/W2997541867","https://openalex.org/W3209085687"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"our":[3,124],"experience":[4],"and":[5,24,54,73,83,99,104],"methodology":[6],"used":[7,44],"in":[8],"the":[9,20,32,37,45,50,55,60,67,78,87,91,95,100,106,111,119],"formal":[10,33],"verification":[11,34,108,121],"of":[12,19,40,69,80,90,117],"an":[13],"industrial":[14],"embedded":[15],"SOC":[16],"product":[17],"composed":[18],"ARM920T":[21],"processor":[22],"core":[23],"16":[25],"function":[26],"modules,":[27],"i.e.,":[28],"IPs.":[29],"We":[30,43],"employed":[31],"to":[35,48,58,123],"verify":[36,59],"RTL":[38,51],"implementation":[39],"each":[41],"module.":[42],"model":[46,53,71,92,101],"checking":[47,57,102],"make":[49],"golden":[52],"equivalence":[56],"following":[61],"refinements.":[62],"Specifically,":[63],"we":[64],"describe":[65],"1)":[66],"selection":[68],"a":[70,74],"checker":[72],"modeling":[75,79],"language,":[76,103],"2)":[77],"multiple":[81],"clocks":[82,85],"gated":[84],"using":[86],"implicit":[88],"clock":[89],"checker,":[93],"3)":[94],"translation":[96],"between":[97],"Verilog":[98],"4)":[105],"module":[107],"strategy":[109,122],"including":[110],"problem":[112],"size":[113],"reduction":[114],"techniques.":[115],"Results":[116],"applying":[118],"proposed":[120],"design":[125],"are":[126],"also":[127],"covered.":[128]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
