{"id":"https://openalex.org/W2121246308","doi":"https://doi.org/10.1109/iccd.1996.563571","title":"Design tradeoffs and experience with Motorola PowerPC migration tools","display_name":"Design tradeoffs and experience with Motorola PowerPC migration tools","publication_year":2002,"publication_date":"2002-12-23","ids":{"openalex":"https://openalex.org/W2121246308","doi":"https://doi.org/10.1109/iccd.1996.563571","mag":"2121246308"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.1996.563571","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1996.563571","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Conference on Computer Design. VLSI in Computers and Processors","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021886781","display_name":"Maur\u00edcio Breternitz","orcid":"https://orcid.org/0000-0003-1752-6255"},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M. Breternitz","raw_affiliation_strings":["RISC Software Division, Motorola, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"RISC Software Division, Motorola, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I1333370159"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036900635","display_name":"A. Manikonda","orcid":null},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Manikonda","raw_affiliation_strings":["RISC Software Division, Motorola, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"RISC Software Division, Motorola, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I1333370159"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003691182","display_name":"M. Ommerman","orcid":null},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Ommerman","raw_affiliation_strings":["RISC Software Division, Motorola, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"RISC Software Division, Motorola, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I1333370159"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080308941","display_name":"W. Su","orcid":null},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Su","raw_affiliation_strings":["RISC Software Division, Motorola, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"RISC Software Division, Motorola, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I1333370159"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038397806","display_name":"Adam Thornton","orcid":null},"institutions":[{"id":"https://openalex.org/I1333370159","display_name":"Motorola (United States)","ror":"https://ror.org/01hafxd32","country_code":"US","type":"company","lineage":["https://openalex.org/I1333370159"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Thornton","raw_affiliation_strings":["RISC Software Division, Motorola, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"RISC Software Division, Motorola, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I1333370159"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5021886781"],"corresponding_institution_ids":["https://openalex.org/I1333370159"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15428506,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"37","issue":null,"first_page":"301","last_page":"308"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/powerpc","display_name":"PowerPC","score":0.9854311943054199},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6603535413742065},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.6564429998397827},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5577384829521179},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.44920575618743896},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4386494755744934},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4237358272075653},{"id":"https://openalex.org/keywords/masking","display_name":"Masking (illustration)","score":0.41450950503349304},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2597053647041321},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14521273970603943},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12702777981758118}],"concepts":[{"id":"https://openalex.org/C56005371","wikidata":"https://www.wikidata.org/wiki/Q209860","display_name":"PowerPC","level":3,"score":0.9854311943054199},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6603535413742065},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.6564429998397827},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5577384829521179},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.44920575618743896},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4386494755744934},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4237358272075653},{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.41450950503349304},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2597053647041321},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14521273970603943},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12702777981758118},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.1996.563571","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1996.563571","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Conference on Computer Design. VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Reduced inequalities","score":0.7699999809265137,"id":"https://metadata.un.org/sdg/10"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1491178396","https://openalex.org/W1599155214","https://openalex.org/W1923162504","https://openalex.org/W2062414399","https://openalex.org/W2066118523","https://openalex.org/W2103940946","https://openalex.org/W2117588798","https://openalex.org/W2163935347","https://openalex.org/W2339669378","https://openalex.org/W3123681665","https://openalex.org/W4252357740"],"related_works":["https://openalex.org/W2184274109","https://openalex.org/W1522250664","https://openalex.org/W2351923666","https://openalex.org/W2599805048","https://openalex.org/W2113329205","https://openalex.org/W1767235216","https://openalex.org/W270299739","https://openalex.org/W386418774","https://openalex.org/W1992604140","https://openalex.org/W2132071463"],"abstract_inverted_index":{"The":[0,34,57],"Motorola":[1],"PowerPC":[2],"migration":[3],"tools":[4],"enable":[5],"the":[6,19,25,41,62],"conversion":[7],"of":[8,37,43,52,59,64],"assembly":[9,30],"programs":[10,31],"from":[11],"other":[12],"architectures":[13],"to":[14,27,32],"PowerPC.":[15,33],"This":[16],"paper":[17],"describes":[18],"design":[20,68],"approach":[21],"and":[22,50,61],"experience":[23],"with":[24],"tool":[26],"translate":[28],"x86":[29],"key":[35],"problems":[36],"handling":[38],"16-bit":[39,45],"code,":[40],"effects":[42,63],"masking":[44],"operations":[46],"into":[47],"32-bit":[48],"registers":[49],"optimization":[51],"condition":[53],"flags":[54],"are":[55,70],"discussed.":[56],"efficiency":[58],"translation":[60],"architectural":[65],"constraints":[66],"on":[67],"tradeoffs":[69],"analyzed.":[71]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}