{"id":"https://openalex.org/W1676228457","doi":"https://doi.org/10.1109/iccd.1988.25723","title":"Microarchitecture of the 80960 high-integration processors","display_name":"Microarchitecture of the 80960 high-integration processors","publication_year":2003,"publication_date":"2003-01-06","ids":{"openalex":"https://openalex.org/W1676228457","doi":"https://doi.org/10.1109/iccd.1988.25723","mag":"1676228457"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.1988.25723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1988.25723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1988 IEEE International Conference on Computer Design: VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058261003","display_name":"G. Hinton","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"G. Hinton","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007659433","display_name":"K. Lai","orcid":"https://orcid.org/0009-0008-6579-7782"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Lai","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057978661","display_name":"R. Steck","orcid":"https://orcid.org/0000-0003-1574-2165"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Steck","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5058261003"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07452509,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"362","last_page":"365"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7564868927001953},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.708296537399292},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.615772008895874},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5970300436019897},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5652143955230713},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4708627760410309},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.41229814291000366}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7564868927001953},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.708296537399292},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.615772008895874},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5970300436019897},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5652143955230713},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4708627760410309},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.41229814291000366},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.1988.25723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1988.25723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1988 IEEE International Conference on Computer Design: VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W122453572","https://openalex.org/W2038503502","https://openalex.org/W2351011383","https://openalex.org/W2146879484","https://openalex.org/W4221002079","https://openalex.org/W1757458251","https://openalex.org/W1980898636","https://openalex.org/W2141090099","https://openalex.org/W2045325972","https://openalex.org/W3008777550"],"abstract_inverted_index":{"The":[0,68],"80960":[1,75],"is":[2],"Intel":[3],"Corporation's":[4],"newest":[5],"microprocessor":[6],"and":[7,23,38,65,77,95,105],"serves":[8],"as":[9,56,58],"the":[10,21,33,71,74,78,86,92,97,101,106],"first":[11,60],"implementation":[12,61],"of":[13,20,73],"a":[14,28,59],"novel":[15],"architecture":[16,24,51],"family.":[17],"Design":[18],"goals":[19],"processor":[22,76],"were":[25],"to":[26,53,84],"maintain":[27],"constant":[29],"cost/benefit":[30],"ratio":[31],"in":[32,41,49,81],"entire":[34],"design":[35,87],"while":[36],"identifying":[37],"minimization":[39],"bottlenecks":[40],"an":[42,50],"overall":[43],"system":[44],"architecture.":[45],"This":[46],"has":[47],"resulted":[48],"suited":[52],"future":[54],"proliferation":[55],"well":[57],"with":[62],"high":[63],"functionality":[64],"good":[66],"performance.":[67],"authors":[69],"describe":[70],"microarchitecture":[72],"tradeoffs":[79],"made":[80],"its":[82],"development":[83],"meet":[85],"goals.":[88],"Features":[89],"discussed":[90],"include":[91],"instruction":[93],"decode":[94],"sequencing,":[96],"integer":[98],"execution":[99,103],"unit,":[100,104],"floating-point":[102],"translation":[107],"lookaside":[108],"buffer.<":[109],"<ETX":[110],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[111],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[112]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}