{"id":"https://openalex.org/W4388937852","doi":"https://doi.org/10.1109/icccnt56998.2023.10308163","title":"Analysis of Area Efficient Parallel FIR Filters using FPGA","display_name":"Analysis of Area Efficient Parallel FIR Filters using FPGA","publication_year":2023,"publication_date":"2023-07-06","ids":{"openalex":"https://openalex.org/W4388937852","doi":"https://doi.org/10.1109/icccnt56998.2023.10308163"},"language":"en","primary_location":{"id":"doi:10.1109/icccnt56998.2023.10308163","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt56998.2023.10308163","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102582639","display_name":"Neelesh Biswas","orcid":null},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Neelesh Biswas","raw_affiliation_strings":["Jadavpur University,Dept. of ETCE,Kolkata,West Bengal,India,700032"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Jadavpur University,Dept. of ETCE,Kolkata,West Bengal,India,700032","institution_ids":["https://openalex.org/I170979836"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016456170","display_name":"Supriya Dhabal","orcid":"https://orcid.org/0000-0001-8524-0385"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Supriya Dhabal","raw_affiliation_strings":["Netaji Subhash Engineering College,Dept. of ECE,Kolkata,West Bengal,India,700152"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Netaji Subhash Engineering College,Dept. of ECE,Kolkata,West Bengal,India,700152","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040273265","display_name":"P. Venkateswaran","orcid":"https://orcid.org/0000-0001-7206-1740"},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Palaniandavar Venkateswaran","raw_affiliation_strings":["Jadavpur University,Dept. of ETCE,Kolkata,West Bengal,India,700032"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Jadavpur University,Dept. of ETCE,Kolkata,West Bengal,India,700032","institution_ids":["https://openalex.org/I170979836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5543,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.6558128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.9191955327987671},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.780899167060852},{"id":"https://openalex.org/keywords/infinite-impulse-response","display_name":"Infinite impulse response","score":0.7466787099838257},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6862653493881226},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.6498746871948242},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.631562352180481},{"id":"https://openalex.org/keywords/half-band-filter","display_name":"Half-band filter","score":0.5066400170326233},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4385940432548523},{"id":"https://openalex.org/keywords/prototype-filter","display_name":"Prototype filter","score":0.4356611967086792},{"id":"https://openalex.org/keywords/linear-filter","display_name":"Linear filter","score":0.4126974940299988},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.4022781550884247},{"id":"https://openalex.org/keywords/filter-design","display_name":"Filter design","score":0.38237905502319336},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3430706560611725},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32201170921325684},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20536234974861145},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09257489442825317},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.08083125948905945}],"concepts":[{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.9191955327987671},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.780899167060852},{"id":"https://openalex.org/C183816354","wikidata":"https://www.wikidata.org/wiki/Q665617","display_name":"Infinite impulse response","level":4,"score":0.7466787099838257},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6862653493881226},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.6498746871948242},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.631562352180481},{"id":"https://openalex.org/C141159389","wikidata":"https://www.wikidata.org/wiki/Q17020444","display_name":"Half-band filter","level":5,"score":0.5066400170326233},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4385940432548523},{"id":"https://openalex.org/C175742284","wikidata":"https://www.wikidata.org/wiki/Q1415537","display_name":"Prototype filter","level":4,"score":0.4356611967086792},{"id":"https://openalex.org/C139722471","wikidata":"https://www.wikidata.org/wiki/Q2619517","display_name":"Linear filter","level":3,"score":0.4126974940299988},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.4022781550884247},{"id":"https://openalex.org/C22597639","wikidata":"https://www.wikidata.org/wiki/Q5449227","display_name":"Filter design","level":3,"score":0.38237905502319336},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3430706560611725},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32201170921325684},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20536234974861145},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09257489442825317},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.08083125948905945},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icccnt56998.2023.10308163","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt56998.2023.10308163","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1183755421","https://openalex.org/W2558324554","https://openalex.org/W2707243777","https://openalex.org/W2773715965","https://openalex.org/W2790557758","https://openalex.org/W2794983611","https://openalex.org/W2907620743","https://openalex.org/W2908535203","https://openalex.org/W2954748826","https://openalex.org/W3007479599","https://openalex.org/W3007785908","https://openalex.org/W3090341123","https://openalex.org/W3119395483","https://openalex.org/W4214900709","https://openalex.org/W4250633431","https://openalex.org/W4280584572","https://openalex.org/W4293868882","https://openalex.org/W6630102723"],"related_works":["https://openalex.org/W3007580271","https://openalex.org/W2129762382","https://openalex.org/W2072565115","https://openalex.org/W4312785053","https://openalex.org/W2810377961","https://openalex.org/W2058863651","https://openalex.org/W3140661709","https://openalex.org/W2493067074","https://openalex.org/W41400205","https://openalex.org/W1538238752"],"abstract_inverted_index":{"Finite":[0],"Impulse":[1,18],"Response":[2,19],"(FIR)":[3],"filters":[4,29,36,77,98],"are":[5,30,66,78,99],"known":[6],"for":[7],"their":[8],"stability":[9],"and":[10,63],"the":[11,32,44,69,106],"reason":[12],"being":[13],"widely":[14],"used":[15,67],"over":[16,34],"Infinite":[17],"(IIR)":[20],"filters.":[21,60],"Out":[22],"of":[23,46,57,72],"many":[24],"FIR":[25,28,50,97],"filters,":[26],"parallel":[27],"chosen":[31],"best":[33],"other":[35],"in":[37],"digital":[38],"signal":[39],"processing.":[40],"This":[41],"paper":[42],"compares":[43],"design":[45,93],"a":[47],"basic":[48,70],"3-parallel":[49],"filter":[51],"as":[52,54,68,105],"well":[53],"two":[55],"versions":[56],"Area-Efficient":[58,76],"3-FIR":[59],"Booth\u2019s":[61],"algorithm":[62],"Carry-look-ahead":[64],"adder":[65],"components":[71],"this":[73],"filter.":[74],"The":[75,84,96],"later":[79,100],"compared":[80],"after":[81],"designing":[82],"them.":[83],"simulation":[85],"has":[86],"been":[87],"carried":[88],"out":[89],"using":[90],"Xilinx":[91],"ISE":[92],"suite":[94],"14.7.":[95],"implemented":[101],"on":[102],"Spartan":[103],"XC6SLX16-2FTG256":[104],"FPGA":[107],"hardware.":[108]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}