{"id":"https://openalex.org/W3093793829","doi":"https://doi.org/10.1109/icccnt49239.2020.9225691","title":"Comparative analysis of 16-tap FIR filter design using different adders","display_name":"Comparative analysis of 16-tap FIR filter design using different adders","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3093793829","doi":"https://doi.org/10.1109/icccnt49239.2020.9225691","mag":"3093793829"},"language":"en","primary_location":{"id":"doi:10.1109/icccnt49239.2020.9225691","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt49239.2020.9225691","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063690928","display_name":"Usha Maddipati","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153924","display_name":"National Institute of Technology Andhra Pradesh","ror":"https://ror.org/0456pcg54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210153924"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Usha Maddipati","raw_affiliation_strings":["Sasi Institute of Technology & Engineering, Tadepalligudem, India"],"affiliations":[{"raw_affiliation_string":"Sasi Institute of Technology & Engineering, Tadepalligudem, India","institution_ids":["https://openalex.org/I4210153924"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011995802","display_name":"Shaik Ahemedali","orcid":null},"institutions":[{"id":"https://openalex.org/I149313025","display_name":"Vignan's Foundation for Science, Technology & Research","ror":"https://ror.org/03bzf1g85","country_code":"IN","type":"education","lineage":["https://openalex.org/I149313025"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shaik Ahemedali","raw_affiliation_strings":["Vignan's Institute of Engineering for Women, Visakhapatnam, India"],"affiliations":[{"raw_affiliation_string":"Vignan's Institute of Engineering for Women, Visakhapatnam, India","institution_ids":["https://openalex.org/I149313025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053416047","display_name":"M. Ramya","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153924","display_name":"National Institute of Technology Andhra Pradesh","ror":"https://ror.org/0456pcg54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210153924"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Maddipati Sri Sai Ramya","raw_affiliation_strings":["Sasi Institute of Technology & Engineering, Tadepalligudem, India"],"affiliations":[{"raw_affiliation_string":"Sasi Institute of Technology & Engineering, Tadepalligudem, India","institution_ids":["https://openalex.org/I4210153924"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112574542","display_name":"M. Devendra Reddy","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153924","display_name":"National Institute of Technology Andhra Pradesh","ror":"https://ror.org/0456pcg54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210153924"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M D Praneeth Reddy","raw_affiliation_strings":["Sasi Institute of Technology & Engineering, Tadepalligudem, India"],"affiliations":[{"raw_affiliation_string":"Sasi Institute of Technology & Engineering, Tadepalligudem, India","institution_ids":["https://openalex.org/I4210153924"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025672227","display_name":"K N J Priya","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153924","display_name":"National Institute of Technology Andhra Pradesh","ror":"https://ror.org/0456pcg54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210153924"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K N J Priya","raw_affiliation_strings":["Sasi Institute of Technology & Engineering, Tadepalligudem, India"],"affiliations":[{"raw_affiliation_string":"Sasi Institute of Technology & Engineering, Tadepalligudem, India","institution_ids":["https://openalex.org/I4210153924"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5063690928"],"corresponding_institution_ids":["https://openalex.org/I4210153924"],"apc_list":null,"apc_paid":null,"fwci":0.7577,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.71435155,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9146572947502136},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.6911424398422241},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6460586190223694},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6042032241821289},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5697547197341919},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.5556763410568237},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5151578187942505},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.46224403381347656},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.4486902356147766},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.4455842077732086},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41824784874916077},{"id":"https://openalex.org/keywords/filter-design","display_name":"Filter design","score":0.41305816173553467},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41151729226112366},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15481135249137878},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15384751558303833},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08498573303222656},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.06920206546783447}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9146572947502136},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.6911424398422241},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6460586190223694},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6042032241821289},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5697547197341919},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.5556763410568237},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5151578187942505},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.46224403381347656},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.4486902356147766},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.4455842077732086},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41824784874916077},{"id":"https://openalex.org/C22597639","wikidata":"https://www.wikidata.org/wiki/Q5449227","display_name":"Filter design","level":3,"score":0.41305816173553467},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41151729226112366},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15481135249137878},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15384751558303833},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08498573303222656},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.06920206546783447},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icccnt49239.2020.9225691","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt49239.2020.9225691","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7300000190734863,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2002797709","https://openalex.org/W2579900540","https://openalex.org/W2783790233","https://openalex.org/W2789795027","https://openalex.org/W2897374949","https://openalex.org/W2907620743","https://openalex.org/W2911206843","https://openalex.org/W2933522286","https://openalex.org/W2971056028","https://openalex.org/W6749095111"],"related_works":["https://openalex.org/W2489015823","https://openalex.org/W2516396101","https://openalex.org/W2186498568","https://openalex.org/W4295540194","https://openalex.org/W2129868416","https://openalex.org/W2364181090","https://openalex.org/W2015457513","https://openalex.org/W4255416339","https://openalex.org/W3082309838","https://openalex.org/W4308935600"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"concentrating":[3],"on":[4,68],"the":[5,44,57,84],"real":[6],"time":[7],"demands":[8],"of":[9,38,79,108],"digital":[10],"signal":[11],"processing,":[12],"a":[13],"delay":[14],"and":[15,73],"power":[16],"efficient":[17],"16-tap":[18],"direct":[19],"form":[20],"low":[21],"pass":[22],"FIR":[23,103],"filter":[24,30,58,104],"is":[25],"realized":[26],"using":[27,34,75,98],"FPGA.":[28],"The":[29,64],"coefficients":[31],"are":[32,54],"generated":[33],"Kaiser":[35],"Window":[36],"function":[37],"MATLAB":[39],"FDA":[40],"tool.":[41],"For":[42],"obtaining":[43],"high":[45],"speed":[46],"operation":[47],"at":[48],"reasonable":[49],"power,":[50],"various":[51,109],"adder":[52,112],"architectures":[53],"considered":[55],"for":[56,102],"design":[59,105],"along":[60],"with":[61],"vedic":[62],"multiplier.":[63],"designs":[65],"were":[66],"implemented":[67],"Artix-7":[69],"xc7a100tcsg324-1":[70],"FPGA":[71],"board":[72],"debugged":[74],"Virtual":[76],"Input/output":[77],"IP":[78],"Xilinx":[80],"Vivado":[81],"to":[82],"validate":[83],"results.":[85],"Experimental":[86],"results":[87],"show":[88],"that":[89,107],"efficiency":[90],"in":[91],"power-delay":[92],"product":[93],"can":[94],"be":[95],"obtained":[96],"by":[97],"Carry":[99],"Increment":[100],"Adder":[101],"than":[106],"other":[110],"multi-bit":[111],"structures.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}