{"id":"https://openalex.org/W3094624852","doi":"https://doi.org/10.1109/icccnt49239.2020.9225404","title":"Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs","display_name":"Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3094624852","doi":"https://doi.org/10.1109/icccnt49239.2020.9225404","mag":"3094624852"},"language":"en","primary_location":{"id":"doi:10.1109/icccnt49239.2020.9225404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt49239.2020.9225404","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082151201","display_name":"Yamini Devi Ykuntam","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145126","display_name":"Aditya Birla (India)","ror":"https://ror.org/03pztks36","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210145126"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Yamini devi Ykuntam","raw_affiliation_strings":["Aditya Engineering college, Surampalem, India"],"affiliations":[{"raw_affiliation_string":"Aditya Engineering college, Surampalem, India","institution_ids":["https://openalex.org/I4210145126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108733819","display_name":"K. Pavani","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145126","display_name":"Aditya Birla (India)","ror":"https://ror.org/03pztks36","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210145126"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Katta Pavani","raw_affiliation_strings":["Aditya Engineering college, Surampalem, India"],"affiliations":[{"raw_affiliation_string":"Aditya Engineering college, Surampalem, India","institution_ids":["https://openalex.org/I4210145126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066872460","display_name":"Krishna Saladi","orcid":"https://orcid.org/0000-0002-7642-5211"},"institutions":[{"id":"https://openalex.org/I4210145126","display_name":"Aditya Birla (India)","ror":"https://ror.org/03pztks36","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210145126"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Krishna Saladi","raw_affiliation_strings":["Aditya Engineering college, Surampalem, India"],"affiliations":[{"raw_affiliation_string":"Aditya Engineering college, Surampalem, India","institution_ids":["https://openalex.org/I4210145126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5082151201"],"corresponding_institution_ids":["https://openalex.org/I4210145126"],"apc_list":null,"apc_paid":null,"fwci":2.2876,"has_fulltext":false,"cited_by_count":54,"citation_normalized_percentile":{"value":0.8876283,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9368147850036621},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.688865065574646},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.6126892566680908},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6071293950080872},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5813771486282349},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5539299249649048},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.533027172088623},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4669559895992279},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.44955193996429443},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3439810872077942},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.342735230922699},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3384857475757599},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.22586199641227722},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.10417672991752625},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06939372420310974}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9368147850036621},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.688865065574646},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.6126892566680908},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6071293950080872},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5813771486282349},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5539299249649048},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.533027172088623},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4669559895992279},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.44955193996429443},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3439810872077942},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.342735230922699},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3384857475757599},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.22586199641227722},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.10417672991752625},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06939372420310974},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icccnt49239.2020.9225404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt49239.2020.9225404","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1515343314","https://openalex.org/W1584139484","https://openalex.org/W2006097283","https://openalex.org/W2014227236","https://openalex.org/W2039636925","https://openalex.org/W2062557453","https://openalex.org/W2122910852","https://openalex.org/W2168543008","https://openalex.org/W2188112511","https://openalex.org/W2474203529","https://openalex.org/W2555599679","https://openalex.org/W2933522286","https://openalex.org/W3212618473","https://openalex.org/W6634913026"],"related_works":["https://openalex.org/W2489015823","https://openalex.org/W2516396101","https://openalex.org/W2186498568","https://openalex.org/W2189403562","https://openalex.org/W4312097652","https://openalex.org/W2352033875","https://openalex.org/W2803703254","https://openalex.org/W2086473731","https://openalex.org/W2370292629","https://openalex.org/W2778027992"],"abstract_inverted_index":{"Major":[0],"operation":[1],"block":[2],"in":[3,35,81,137,166],"any":[4],"processing":[5],"unit":[6],"is":[7,33,55,79,95],"a":[8,72],"multiplier.":[9],"There":[10],"are":[11,15,110,132,145,158],"many":[12],"multiplication":[13,27,31],"algorithms":[14],"proposed,":[16],"by":[17,97],"using":[18,112,134,147,152],"which":[19],"multiplier":[20,66,78,108,130,164],"structure":[21,74],"can":[22],"be":[23],"designed.":[24],"Among":[25],"various":[26],"algorithms,":[28],"Wallace":[29,64,76,106],"tree":[30,65,77,107],"algorithm":[32],"beneficial":[34],"terms":[36,167],"of":[37,39,44,63,75,92,168,171],"speed":[38,51,62],"operation.":[40],"With":[41],"the":[42,61,85,88,129],"advancement":[43],"technology,":[45],"demand":[46],"for":[47],"circuits":[48],"with":[49,160],"high":[50],"and":[52,124,150,173],"low":[53],"area":[54,70,169],"increasing.":[56],"In":[57,84,102],"order":[58],"to":[59,162],"improve":[60],"without":[67],"degrading":[68],"its":[69],"parameter,":[71],"new":[73],"proposed":[80,86,111,143,156],"this":[82,103],"paper.":[83],"structure,":[87],"final":[89],"addition":[90],"stage":[91],"partial":[93],"products":[94],"performed":[96],"parallel":[98],"prefix":[99],"adders":[100],"(PPAs).":[101],"paper,":[104],"five":[105],"structures":[109,131,144],"Kogge":[113],"stone":[114],"adder,":[115,117,120],"Sklansky":[116],"Brent":[118],"Kung":[119],"Ladner":[121],"Fischer":[122],"adder":[123],"Han":[125],"carlson":[126],"adder.":[127],"All":[128],"designed":[133],"Verilog":[135],"HDL":[136],"Xilinix":[138],"13.2":[139],"design":[140,165],"suite.":[141],"The":[142,155],"simulated":[146],"ISIM":[148],"simulator":[149],"synthesized":[151],"XST":[153],"synthesizer.":[154],"designs":[157],"analyzed":[159],"respect":[161],"traditional":[163],"(No.":[170],"LUTs)":[172],"delay":[174],"(ns).":[175]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":13},{"year":2024,"cited_by_count":18},{"year":2023,"cited_by_count":11},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":5}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}