{"id":"https://openalex.org/W2997408777","doi":"https://doi.org/10.1109/icccnt45670.2019.8944848","title":"Design and Verification of Three Phase Sequence Decomposer on Re-configurable Hardware","display_name":"Design and Verification of Three Phase Sequence Decomposer on Re-configurable Hardware","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W2997408777","doi":"https://doi.org/10.1109/icccnt45670.2019.8944848","mag":"2997408777"},"language":"en","primary_location":{"id":"doi:10.1109/icccnt45670.2019.8944848","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt45670.2019.8944848","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101818671","display_name":"Praveen Kumar","orcid":"https://orcid.org/0000-0003-2751-9040"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Praveen Kumar","raw_affiliation_strings":["Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060626269","display_name":"Aishwarya Mittal","orcid":null},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aishwarya Mittal","raw_affiliation_strings":["Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072998967","display_name":"Kakarla Uday Kanth Reddy","orcid":null},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kakarla Uday Kanth Reddy","raw_affiliation_strings":["Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062670384","display_name":"Shubham Chowdhary","orcid":null},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shubham Chowdhary","raw_affiliation_strings":["Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070745216","display_name":"Vishal Kumar","orcid":"https://orcid.org/0000-0002-5055-1447"},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vishal Kumar","raw_affiliation_strings":["Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077104071","display_name":"Rajendra Pratap","orcid":null},"institutions":[{"id":"https://openalex.org/I154851008","display_name":"Indian Institute of Technology Roorkee","ror":"https://ror.org/00582g326","country_code":"IN","type":"education","lineage":["https://openalex.org/I154851008"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajendra Pratap","raw_affiliation_strings":["Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrica Engineering, Indian Institute of Technology, Roorkee, India","institution_ids":["https://openalex.org/I154851008"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I154851008"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10223","display_name":"Microgrid Control and Optimization","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10223","display_name":"Microgrid Control and Optimization","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8230427503585815},{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.7363872528076172},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6867548227310181},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.5528362989425659},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.5065439939498901},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4623509645462036},{"id":"https://openalex.org/keywords/decomposer","display_name":"Decomposer","score":0.41420888900756836},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4032652676105499},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.18325939774513245}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8230427503585815},{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.7363872528076172},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6867548227310181},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.5528362989425659},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.5065439939498901},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4623509645462036},{"id":"https://openalex.org/C104170005","wikidata":"https://www.wikidata.org/wiki/Q842391","display_name":"Decomposer","level":3,"score":0.41420888900756836},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4032652676105499},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.18325939774513245},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C110872660","wikidata":"https://www.wikidata.org/wiki/Q37813","display_name":"Ecosystem","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icccnt45670.2019.8944848","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icccnt45670.2019.8944848","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1413033981","https://openalex.org/W1903282549","https://openalex.org/W1971363881","https://openalex.org/W2010416873","https://openalex.org/W2016648726","https://openalex.org/W2153473157","https://openalex.org/W2153597540","https://openalex.org/W2158551853","https://openalex.org/W2159017290","https://openalex.org/W2734851642","https://openalex.org/W2798557877","https://openalex.org/W2895849490"],"related_works":["https://openalex.org/W2080235730","https://openalex.org/W2534868112","https://openalex.org/W2694160303","https://openalex.org/W4297665406","https://openalex.org/W3028347934","https://openalex.org/W2387631519","https://openalex.org/W2749962643","https://openalex.org/W2784192210","https://openalex.org/W2185692674","https://openalex.org/W2973221965"],"abstract_inverted_index":{"In":[0],"power":[1,60],"systems,":[2],"the":[3,12,50,74,98,107,122,127,136,143,147,156,173,185,190],"analysis":[4],"of":[5,14,39,54,80,96,106,126,146,189],"multi-phase":[6],"systems":[7],"generally":[8],"takes":[9],"place":[10],"with":[11],"help":[13],"sequence":[15,69,82,192],"components.":[16],"A":[17],"balanced":[18],"system":[19,61],"can":[20],"always":[21],"be":[22],"analyzed":[23],"on":[24,85,155],"a":[25,55,59,81],"per-phase":[26],"basis":[27],"but":[28],"to":[29,120],"account":[30],"for":[31,142],"various":[32],"other":[33],"cases":[34],"viz.":[35,100],"control":[36,47],"and":[37,46,48,52,77,103,187],"operation":[38],"grid-connected":[40],"devices":[41],"(thorough":[42,63],"positive":[43],"sequences),":[44],"protection":[45],"determining":[49],"type":[51],"location":[53],"fault":[56],"appearing":[57],"in":[58],"network":[62],"negative":[64,102],"sequences)":[65],"is":[66,94,130,140,153,165],"done":[67],"using":[68,132,167],"component.":[70],"This":[71],"paper":[72],"presents":[73],"design,":[75],"verification":[76,125,145],"real-time":[78,144],"implementation":[79],"decomposer":[83],"(SD)":[84],"reconfigurable":[86],"hardware":[87,179],"i.e.":[88],"Field-Programming":[89],"Gate":[90],"Array":[91],"(FPGA)":[92],"that":[93],"capable":[95],"extracting":[97],"sequences":[99,105],"positive,":[101],"zero":[104],"three-phase":[108],"unbalanced":[109],"systems.":[110],"Xilinx":[111,157],"Integrated":[112],"Synthesis":[113],"Environment":[114],"(ISE)":[115],"12.4,":[116],"has":[117],"been":[118],"used":[119,141],"implement":[121],"design.":[123],"The":[124,150,162],"developed":[128,148],"design":[129,152,164],"verified":[131],"ModelSim":[133],"simulator,":[134],"whereas":[135],"ChipScope":[137],"Pro":[138],"Analyzer":[139],"SD.":[149],"proposed":[151,191],"targeted":[154],"Virtex-5,":[158],"FPGA":[159],"development":[160],"board.":[161],"complete":[163],"implemented":[166],"fixed-point":[168],"integer":[169],"arithmetic":[170],"which":[171],"reduces":[172],"computational":[174],"burden":[175],"as":[176,178],"well":[177],"resource":[180],"utilization.":[181],"Experimental":[182],"results":[183],"confirm":[184],"accuracy":[186],"feasibility":[188],"decomposer.":[193]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
