{"id":"https://openalex.org/W4416429826","doi":"https://doi.org/10.1109/iccad66269.2025.11241013","title":"Invited Paper: End-to-end RFIC Topology Synthesis and Design combining Reinforcement learning and Inverse Design","display_name":"Invited Paper: End-to-end RFIC Topology Synthesis and Design combining Reinforcement learning and Inverse Design","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416429826","doi":"https://doi.org/10.1109/iccad66269.2025.11241013"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11241013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11241013","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086851941","display_name":"Kaushik Sengupta","orcid":"https://orcid.org/0000-0001-7074-0248"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kaushik Sengupta","raw_affiliation_strings":["Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA"],"affiliations":[{"raw_affiliation_string":"Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091453526","display_name":"Jonathan Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Zhou","raw_affiliation_strings":["Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA"],"affiliations":[{"raw_affiliation_string":"Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080815432","display_name":"Emir Ali Karahan","orcid":"https://orcid.org/0009-0007-1515-4271"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Emir Ali Karahan","raw_affiliation_strings":["Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA"],"affiliations":[{"raw_affiliation_string":"Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036133306","display_name":"Juho Park","orcid":"https://orcid.org/0000-0001-8228-741X"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Juho Park","raw_affiliation_strings":["Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA"],"affiliations":[{"raw_affiliation_string":"Princeton University,Electrical and Computer Engineering,Princeton,NJ,USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5086851941"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.3439943,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.325300008058548,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.325300008058548,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.14309999346733093,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11392","display_name":"Energy Harvesting in Wireless Networks","score":0.13269999623298645,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rfic","display_name":"RFIC","score":0.8201000094413757},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5618000030517578},{"id":"https://openalex.org/keywords/design-process","display_name":"Design process","score":0.4530999958515167},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.44350001215934753},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4392000138759613},{"id":"https://openalex.org/keywords/engineering-design-process","display_name":"Engineering design process","score":0.43709999322891235},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.43230000138282776},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4124999940395355},{"id":"https://openalex.org/keywords/electromagnetics","display_name":"Electromagnetics","score":0.4083000123500824},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.40529999136924744}],"concepts":[{"id":"https://openalex.org/C121152627","wikidata":"https://www.wikidata.org/wiki/Q6095735","display_name":"RFIC","level":3,"score":0.8201000094413757},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6104000210762024},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5618000030517578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49889999628067017},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.4530999958515167},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.44350001215934753},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4392000138759613},{"id":"https://openalex.org/C34972735","wikidata":"https://www.wikidata.org/wiki/Q2920267","display_name":"Engineering design process","level":2,"score":0.43709999322891235},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.43230000138282776},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4124999940395355},{"id":"https://openalex.org/C2909720056","wikidata":"https://www.wikidata.org/wiki/Q11406","display_name":"Electromagnetics","level":2,"score":0.4083000123500824},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.40529999136924744},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4049000144004822},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3950999975204468},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3871999979019165},{"id":"https://openalex.org/C106246047","wikidata":"https://www.wikidata.org/wiki/Q4928435","display_name":"Iterative design","level":3,"score":0.353300005197525},{"id":"https://openalex.org/C207467116","wikidata":"https://www.wikidata.org/wiki/Q4385666","display_name":"Inverse","level":2,"score":0.3492000102996826},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3328999876976013},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.314300000667572},{"id":"https://openalex.org/C184408114","wikidata":"https://www.wikidata.org/wiki/Q1502022","display_name":"Generative Design","level":3,"score":0.2912999987602234},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2912999987602234},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.2867000102996826},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.2833999991416931},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.28049999475479126},{"id":"https://openalex.org/C124216869","wikidata":"https://www.wikidata.org/wiki/Q7621833","display_name":"Design strategy","level":2,"score":0.2775000035762787},{"id":"https://openalex.org/C91748784","wikidata":"https://www.wikidata.org/wiki/Q11406","display_name":"Electromagnetism","level":2,"score":0.2712000012397766},{"id":"https://openalex.org/C143587482","wikidata":"https://www.wikidata.org/wiki/Q1543216","display_name":"Iterative and incremental development","level":2,"score":0.2648000121116638},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.26440000534057617},{"id":"https://openalex.org/C120823896","wikidata":"https://www.wikidata.org/wiki/Q1043226","display_name":"Product design","level":3,"score":0.26339998841285706},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.26179999113082886},{"id":"https://openalex.org/C2777466363","wikidata":"https://www.wikidata.org/wiki/Q17008971","display_name":"Design tool","level":2,"score":0.26170000433921814},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.2614000141620636},{"id":"https://openalex.org/C110367647","wikidata":"https://www.wikidata.org/wiki/Q497166","display_name":"Metamaterial","level":2,"score":0.2599000036716461}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11241013","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11241013","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320337345","display_name":"Office of Naval Research","ror":"https://ror.org/00rk2pe57"},{"id":"https://openalex.org/F4320338279","display_name":"Air Force Office of Scientific Research","ror":"https://ror.org/011e9bt93"},{"id":"https://openalex.org/F4320338281","display_name":"Army Research Office","ror":"https://ror.org/05epdh915"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1569638374","https://openalex.org/W2172135569","https://openalex.org/W2626403730","https://openalex.org/W2755324911","https://openalex.org/W2770880660","https://openalex.org/W2811492602","https://openalex.org/W2903983414","https://openalex.org/W3015344750","https://openalex.org/W3092323705","https://openalex.org/W3113108189","https://openalex.org/W4285193267","https://openalex.org/W4285451629","https://openalex.org/W4296912594","https://openalex.org/W4378194784","https://openalex.org/W4385826751","https://openalex.org/W4401111186","https://openalex.org/W4402978799","https://openalex.org/W4405893155","https://openalex.org/W4408164433","https://openalex.org/W4408183242","https://openalex.org/W4409346832","https://openalex.org/W4410737671","https://openalex.org/W4412624231","https://openalex.org/W4413122014","https://openalex.org/W4413122368","https://openalex.org/W4413122521"],"related_works":[],"abstract_inverted_index":{"Distinct":[0],"from":[1,51,82,166],"low-frequency":[2],"analog":[3],"design,":[4],"design":[5,36,80,126,133,151,163,173,199,206],"of":[6,76,102,140,227,230,245],"radio-frequency,":[7],"millimeter-wave":[8],"and":[9,20,32,67,99,105,119,131,159,164,183,186,207,221,236],"terahertz":[10],"frequency":[11],"chips":[12],"follows":[13],"a":[14,111,138,144,148,170,194,204],"complex":[15,156],"co-design":[16],"process":[17,37,81],"between":[18],"circuits":[19,182],"electromagnetics":[21],"(EM).":[22],"These":[23,108],"two":[24],"domains":[25],"are":[26,218],"strongly":[27],"coupled":[28],"to":[29,41,58,84,86],"each":[30],"other,":[31],"this":[33,128,202,217],"makes":[34],"the":[35,77,177,189,228,243,246],"extremely":[38,90],"complex.":[39],"Similar":[40],"circuit":[42,104,184],"topologies,":[43],"EM":[44,106],"topologies":[45],"can":[46,88,154,224],"be":[47,89],"very":[48],"diverse":[49],"ranging":[50],"lumped":[52],"elements":[53,75],"such":[54,62],"as":[55,63],"inductors,":[56],"capacitors":[57],"distributed":[59],"passive":[60],"structures":[61,158,192],"transmission":[64],"lines,":[65],"antennas,":[66],"all":[68],"possible":[69],"combinations,":[70],"taking":[71],"one":[72],"or":[73],"more":[74],"set.":[78],"The":[79,212],"ideation":[83],"schematic":[85],"layout":[87,165],"time-consuming":[91],"relying":[92],"heavily":[93],"on":[94],"expert":[95],"knowledge,":[96],"manual":[97],"interventions,":[98],"iterative":[100],"tuning":[101],"predefined":[103],"topologies.":[107,232],"methods":[109],"follow":[110],"bottom-up":[112],"approach,":[113],"starting":[114],"with":[115],"fixed":[116],"geometric":[117],"templates":[118],"using":[120],"trial-and-error":[121],"optimization.":[122],"Other":[123],"than":[124],"long":[125],"times,":[127],"limits":[129],"innovation":[130],"accessible":[132],"spaces.":[134],"Here,":[135],"we":[136],"present":[137,169,234],"series":[139],"approaches":[141],"that":[142,153,175,214],"introduce":[143],"fundamentally":[145],"different":[146],"strategy:":[147],"universal":[149],"inverse":[150,198],"method":[152],"generate":[155],"electromagnetic":[157,191],"subsequently":[160],"fabrication-ready":[161],"RFIC":[162,180],"specifications.":[167],"We":[168,233],"reinforcement":[171],"learning":[172,196],"framework":[174],"canvasses":[176],"space":[178],"for":[179,210],"topology,":[181],"parameters":[185],"then":[187],"synthesizes":[188],"interface":[190],"through":[193,216],"deep":[195],"enabled":[197],"framework.":[200],"Collaboratively,":[201],"creates":[203],"specifications-to-GDS":[205],"synthesis":[208],"flow":[209],"RFICs.":[211],"designs":[213],"emerge":[215],"often":[219],"non-traditional":[220],"non-intuitive,":[222],"but":[223],"break":[225],"many":[226],"trade-offs":[229],"known":[231],"fabricated":[235],"measured":[237],"results":[238],"in":[239],"silicon":[240],"ICs":[241],"demonstrating":[242],"feasibility":[244],"presented":[247],"approaches.":[248]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-11-20T00:00:00"}