{"id":"https://openalex.org/W4416429589","doi":"https://doi.org/10.1109/iccad66269.2025.11240935","title":"Capacitance Extraction via Machine Learning with Application to Interconnect Geometry Exploration","display_name":"Capacitance Extraction via Machine Learning with Application to Interconnect Geometry Exploration","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416429589","doi":"https://doi.org/10.1109/iccad66269.2025.11240935"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028459162","display_name":"Cheng\u2010Yu Tsai","orcid":"https://orcid.org/0000-0001-6150-4577"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Yu Tsai","raw_affiliation_strings":["Georgia Institute of Technology,Atlanta,Georgia,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology,Atlanta,Georgia,USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Suwan Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Suwan Kim","raw_affiliation_strings":["Samsung Electronics,Suwon,South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics,Suwon,South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung-Kyu Lim","raw_affiliation_strings":["Georgia Institute of Technology,Atlanta,Georgia,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology,Atlanta,Georgia,USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.4704,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.92574838,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6884999871253967,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6884999871253967,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.07460000365972519,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.054099999368190765,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8309999704360962},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.7860000133514404},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.6671000123023987},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5594000220298767},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.4936999976634979},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4894999861717224},{"id":"https://openalex.org/keywords/parasitic-capacitance","display_name":"Parasitic capacitance","score":0.47380000352859497},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4453999996185303}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8309999704360962},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.7860000133514404},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.6671000123023987},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5594000220298767},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.4936999976634979},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4894999861717224},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4790000021457672},{"id":"https://openalex.org/C154318817","wikidata":"https://www.wikidata.org/wiki/Q2157249","display_name":"Parasitic capacitance","level":4,"score":0.47380000352859497},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4453999996185303},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.41690000891685486},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41019999980926514},{"id":"https://openalex.org/C4725764","wikidata":"https://www.wikidata.org/wiki/Q844704","display_name":"Extraction (chemistry)","level":2,"score":0.40619999170303345},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.39590001106262207},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.39419999718666077},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.3847000002861023},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.36320000886917114},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3582000136375427},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.3375999927520752},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.33160001039505005},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.304500013589859},{"id":"https://openalex.org/C108882727","wikidata":"https://www.wikidata.org/wiki/Q2991685","display_name":"Solid modeling","level":2,"score":0.30230000615119934},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.29840001463890076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29809999465942383},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.29030001163482666},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2824999988079071},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2815000116825104},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.2750999927520752},{"id":"https://openalex.org/C52622490","wikidata":"https://www.wikidata.org/wiki/Q1026626","display_name":"Feature extraction","level":2,"score":0.2685999870300293},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2599000036716461}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1585690183","https://openalex.org/W2068702789","https://openalex.org/W2126924619","https://openalex.org/W2142992648","https://openalex.org/W2163269926","https://openalex.org/W2948549627","https://openalex.org/W2949676527","https://openalex.org/W3041504479","https://openalex.org/W3178067780","https://openalex.org/W4206479137","https://openalex.org/W4221034897","https://openalex.org/W4233525618","https://openalex.org/W4244352942","https://openalex.org/W4403676982","https://openalex.org/W4408151733"],"related_works":[],"abstract_inverted_index":{"As":[0],"Moore\u2019s":[1],"law":[2],"slows":[3],"down,":[4],"foundries":[5],"and":[6,148],"design":[7,12],"houses":[8],"are":[9,44],"resorting":[10],"to":[11,16,47,49,61,111],"technology":[13,23],"co-optimization":[14],"(DTCO)":[15],"squeeze":[17],"more":[18],"performance":[19],"out":[20],"of":[21,28],"a":[22,32,50,63,67,90],"node.":[24],"However,":[25],"the":[26,79,112,130,145,149],"efficiency":[27],"EDA":[29],"tools":[30,43],"plays":[31],"key":[33],"role":[34],"in":[35],"driving":[36],"DTCO.":[37,84],"The":[38],"existing":[39,73],"commercial":[40,74],"parasitic":[41,64,101],"extraction":[42,116],"not":[45],"able":[46],"respond":[48],"process":[51],"parameter":[52],"change":[53,71],"efficiently.":[54],"For":[55],"example,":[56],"it":[57],"takes":[58],"25":[59],"minutes":[60],"re-generate":[62],"netlist":[65],"for":[66,81,144],"mere":[68],"layer":[69,157],"thickness":[70,158],"using":[72],"tools.":[75],"This":[76],"runtime":[77],"becomes":[78],"bottleneck":[80],"standard":[82,95,138],"cell":[83,139],"In":[85],"this":[86],"work,":[87],"we":[88],"demonstrate":[89],"machine-learning-based":[91],"method":[92],"targeted":[93],"on":[94],"cells":[96],"that":[97],"can":[98,151],"efficiently":[99],"extract":[100,134],"capacitance":[102,154],"within":[103,159],"seconds":[104],"while":[105],"maintaining":[106],"competitive":[107],"error":[108],"distribution":[109],"compared":[110],"state-of-the-art":[113],"rule-based":[114],"2.5D":[115],"method,":[117],"which":[118],"suffers":[119],"from":[120,136],"pattern":[121],"mismatch":[122],"since":[123],"no":[124],"real":[125],"layout":[126],"is":[127],"provided":[128],"at":[129],"pre-characterization":[131],"stage.":[132],"We":[133],"patterns":[135],"actual":[137],"layouts":[140],"as":[141],"training":[142],"data":[143],"ML":[146],"model,":[147],"model":[150],"predict":[152],"coupling":[153],"with":[155],"unseen":[156],"milliseconds.":[160]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-11-20T00:00:00"}