{"id":"https://openalex.org/W4416429525","doi":"https://doi.org/10.1109/iccad66269.2025.11240927","title":"Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization","display_name":"Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416429525","doi":"https://doi.org/10.1109/iccad66269.2025.11240927"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Jiun-Hao Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jiun-Hao Chen","raw_affiliation_strings":["National Taiwan University,Graduate School of Advanced Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate School of Advanced Technology","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078604015","display_name":"Jie-Hong R. Jiang","orcid":"https://orcid.org/0000-0002-2279-4732"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jie-Hong R. Jiang","raw_affiliation_strings":["National Taiwan University,Graduate School of Advanced Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate School of Advanced Technology","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["University of California,Department of EECS,Berkeley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California,Department of EECS,Berkeley","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.5950000286102295,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.5950000286102295,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.2944999933242798,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.048700001090765,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.5407999753952026},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5031999945640564},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.4309000074863434},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.42559999227523804},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42410001158714294},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.42329999804496765},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.38019999861717224},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.37049999833106995}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7146999835968018},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.5407999753952026},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5031999945640564},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46320000290870667},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.44859999418258667},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.4309000074863434},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.42559999227523804},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42410001158714294},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.42329999804496765},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.38019999861717224},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3709000051021576},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.37049999833106995},{"id":"https://openalex.org/C2778755073","wikidata":"https://www.wikidata.org/wiki/Q10858537","display_name":"Scale (ratio)","level":2,"score":0.35850000381469727},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.35530000925064087},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.334199994802475},{"id":"https://openalex.org/C45237549","wikidata":"https://www.wikidata.org/wiki/Q1376796","display_name":"Restructuring","level":2,"score":0.32659998536109924},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31850001215934753},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3009999990463257},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.2937000095844269},{"id":"https://openalex.org/C78382760","wikidata":"https://www.wikidata.org/wiki/Q2288649","display_name":"Concurrent engineering","level":3,"score":0.289000004529953},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.28369998931884766},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.2791000008583069},{"id":"https://openalex.org/C2778348673","wikidata":"https://www.wikidata.org/wiki/Q739302","display_name":"Production (economics)","level":2,"score":0.2694999873638153},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.26190000772476196},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.25110000371932983}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240927","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240927","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320331164","display_name":"National Science and Technology Council","ror":"https://ror.org/00wnb9798"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1528837436","https://openalex.org/W1993932586","https://openalex.org/W2018989845","https://openalex.org/W2078174680","https://openalex.org/W2106950603","https://openalex.org/W2123710050","https://openalex.org/W2145126108","https://openalex.org/W2169837676","https://openalex.org/W2346205343","https://openalex.org/W2427843410","https://openalex.org/W2941700911","https://openalex.org/W4213162744","https://openalex.org/W4232487136","https://openalex.org/W4239323126","https://openalex.org/W4250065760","https://openalex.org/W4255659196","https://openalex.org/W4389166774","https://openalex.org/W4393145469","https://openalex.org/W4408151478"],"related_works":[],"abstract_inverted_index":{"When":[0],"traditional":[1],"logic":[2],"synthesis":[3,12,22],"algorithms":[4,23],"reach":[5],"saturation,":[6],"yet":[7],"the":[8,56,68,74,83,86],"demand":[9],"for":[10],"improved":[11],"quality":[13],"remains":[14],"high,":[15],"research":[16],"focus":[17],"shifts":[18],"toward":[19],"identifying":[20],"synergistic":[21],"and":[24,99],"efficient":[25],"deployment":[26],"strategies.":[27],"This":[28],"paper":[29],"proposes":[30],"a":[31,39,61],"novel":[32],"rewiring":[33,77],"method":[34,57],"that":[35,66],"can":[36],"substantially":[37],"restructure":[38],"circuit":[40,69],"using":[41],"truth":[42],"tables,":[43],"though":[44],"it":[45],"does":[46],"not":[47],"scale":[48],"beyond":[49],"16":[50],"inputs.":[51],"To":[52],"address":[53],"this":[54],"limitation,":[55],"is":[58],"integrated":[59],"with":[60],"new":[62],"concurrent":[63],"resynthesis":[64],"framework":[65],"partitions":[67],"into":[70],"support-limited":[71],"subcircuits,":[72],"enabling":[73],"application":[75],"of":[76,85],"at":[78],"scale.":[79],"Experimental":[80],"results":[81],"demonstrate":[82],"effectiveness":[84],"proposed":[87],"approach":[88],"in":[89],"minimizing":[90],"various":[91],"cost":[92],"functions,":[93],"including":[94],"node":[95],"count,":[96,98],"transistor":[97],"area":[100],"after":[101],"standard-cell":[102],"mapping,":[103],"achieving":[104],"substantial":[105],"improvements":[106],"over":[107],"strong":[108],"baselines.":[109]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-11-20T00:00:00"}
