{"id":"https://openalex.org/W4416429733","doi":"https://doi.org/10.1109/iccad66269.2025.11240914","title":"Leveraging GPU for Better Detailed Placement Quality","display_name":"Leveraging GPU for Better Detailed Placement Quality","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416429733","doi":"https://doi.org/10.1109/iccad66269.2025.11240914"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240914","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101326899","display_name":"Chen-Han Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen-Han Lu","raw_affiliation_strings":["National Tsing Hua University,Department of Computer Science,Hsinchu,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University,Department of Computer Science,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100429106","display_name":"Wenhao Liu","orcid":"https://orcid.org/0000-0001-9757-1077"},"institutions":[{"id":"https://openalex.org/I1304085615","display_name":"Nvidia (United Kingdom)","ror":"https://ror.org/02kr42612","country_code":"GB","type":"company","lineage":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wen-Hao Liu","raw_affiliation_strings":["Research Nvidia,Hsinchu,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research Nvidia,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I1304085615"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029928585","display_name":"Haoxing Ren","orcid":"https://orcid.org/0000-0003-1028-3860"},"institutions":[{"id":"https://openalex.org/I1304085615","display_name":"Nvidia (United Kingdom)","ror":"https://ror.org/02kr42612","country_code":"GB","type":"company","lineage":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]},{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Haoxing Ren","raw_affiliation_strings":["Research Nvidia,Austin,Texas,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research Nvidia,Austin,Texas,USA","institution_ids":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073705099","display_name":"Ting-Chi Wang","orcid":"https://orcid.org/0000-0002-3435-0418"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ting-Chi Wang","raw_affiliation_strings":["National Tsing Hua University,Department of Computer Science,Hsinchu,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University,Department of Computer Science,Hsinchu,Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5352,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.73042079,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9003000259399414,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9003000259399414,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.04100000113248825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.012500000186264515,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6238999962806702},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5618000030517578},{"id":"https://openalex.org/keywords/position","display_name":"Position (finance)","score":0.47780001163482666},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.4742000102996826},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.46320000290870667},{"id":"https://openalex.org/keywords/focus","display_name":"Focus (optics)","score":0.438400000333786},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.41519999504089355},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.39910000562667847},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.38510000705718994}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6798999905586243},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6238999962806702},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5618000030517578},{"id":"https://openalex.org/C198082294","wikidata":"https://www.wikidata.org/wiki/Q3399648","display_name":"Position (finance)","level":2,"score":0.47780001163482666},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.4742000102996826},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4636000096797943},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.46320000290870667},{"id":"https://openalex.org/C192209626","wikidata":"https://www.wikidata.org/wiki/Q190909","display_name":"Focus (optics)","level":2,"score":0.438400000333786},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.41519999504089355},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.39910000562667847},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.38510000705718994},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3718999922275543},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.3433000147342682},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.32429999113082886},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.3156999945640564},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.2978000044822693},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.2930999994277954},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.2922999858856201},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.28839999437332153},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.28630000352859497},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.2816999852657318},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2782000005245209},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2703000009059906},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.2669999897480011},{"id":"https://openalex.org/C182306322","wikidata":"https://www.wikidata.org/wiki/Q1779371","display_name":"Order (exchange)","level":2,"score":0.26579999923706055},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.26579999923706055},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26330000162124634},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.26019999384880066}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240914","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240914","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1967661769","https://openalex.org/W2014631148","https://openalex.org/W2017814306","https://openalex.org/W2075321943","https://openalex.org/W2116319078","https://openalex.org/W2133838018","https://openalex.org/W2146232231","https://openalex.org/W2167190617","https://openalex.org/W2175238470","https://openalex.org/W2342916071","https://openalex.org/W2568918782","https://openalex.org/W2624122313","https://openalex.org/W2901994323","https://openalex.org/W2997936488","https://openalex.org/W3005126554","https://openalex.org/W3036696276","https://openalex.org/W3141126213","https://openalex.org/W4234143391","https://openalex.org/W4235035338","https://openalex.org/W4249014856","https://openalex.org/W4293023239","https://openalex.org/W4390187368"],"related_works":[],"abstract_inverted_index":{"In":[0,64],"the":[1,51,131],"physical":[2],"design":[3],"flow,":[4],"detailed":[5,28,71,118],"placement":[6,29,40,72],"is":[7],"critical":[8],"for":[9],"wirelength":[10,20,55,120],"optimization":[11,47],"and":[12,77,121,126],"routability":[13,115],"enhancement.":[14],"While":[15],"many":[16],"CPU-based":[17],"approaches":[18,23],"emphasize":[19],"reduction,":[21],"GPU-based":[22,70],"primarily":[24],"focus":[25],"on":[26,106],"accelerating":[27],"without":[30],"sacrificing":[31],"quality.":[32],"However,":[33],"leveraging":[34],"GPU":[35],"parallelism":[36],"to":[37,130],"further":[38,58],"improve":[39],"quality":[41],"remains":[42],"largely":[43],"underexplored.":[44],"As":[45],"existing":[46],"steps":[48],"have":[49],"approached":[50],"practical":[52],"limits":[53],"of":[54,100],"optimization,":[56],"achieving":[57],"improvements":[59],"has":[60],"become":[61],"increasingly":[62],"challenging.":[63],"this":[65],"work,":[66],"we":[67],"propose":[68],"a":[69,82,101],"flow":[73],"featuring":[74],"Simultaneous":[75],"Row":[76],"Order":[78],"Assignment":[79],"(SROA)":[80],"step,":[81],"novel":[83],"step":[84],"that":[85,111],"integrates":[86],"dynamic":[87],"programming-based":[88],"row":[89],"assignment":[90],"with":[91],"heuristic-based":[92],"cell":[93],"position":[94],"adjustment.":[95],"SROA":[96],"enables":[97],"efficient":[98],"exploration":[99],"significantly":[102],"larger":[103],"solution":[104],"space":[105],"GPUs.":[107],"Experimental":[108],"results":[109],"show":[110],"our":[112],"approach":[113],"preserves":[114],"while":[116],"reducing":[117],"routing":[119],"via":[122],"count":[123],"by":[124],"1.35%":[125],"1.03%,":[127],"respectively,":[128],"compared":[129],"ABCDPlace":[132],"solutions.":[133]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-11-20T00:00:00"}