{"id":"https://openalex.org/W4416429516","doi":"https://doi.org/10.1109/iccad66269.2025.11240800","title":"Optimizing SFQ Circuit Design: A Timing-Driven Framework for Performance-Constrained Area Minimization","display_name":"Optimizing SFQ Circuit Design: A Timing-Driven Framework for Performance-Constrained Area Minimization","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416429516","doi":"https://doi.org/10.1109/iccad66269.2025.11240800"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027304745","display_name":"Robert S. Aviles","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert S. Aviles","raw_affiliation_strings":["University of Southern California,Ming Hsieh Department of ECE,Los Angeles,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Southern California,Ming Hsieh Department of ECE,Los Angeles,CA,USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087151326","display_name":"Rassul Bairamkulov","orcid":"https://orcid.org/0000-0001-6783-0664"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Rassul Bairamkulov","raw_affiliation_strings":["EPFL,Lausanne,VD,Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EPFL,Lausanne,VD,Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112926062","display_name":"Ziyu Liu","orcid":"https://orcid.org/0000-0002-3542-6832"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ziyu Liu","raw_affiliation_strings":["University of Southern California,Ming Hsieh Department of ECE,Los Angeles,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Southern California,Ming Hsieh Department of ECE,Los Angeles,CA,USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084205024","display_name":"Peter A. Beerel","orcid":"https://orcid.org/0000-0002-8283-0168"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter A. Beerel","raw_affiliation_strings":["University of Southern California,Ming Hsieh Department of ECE,Los Angeles,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Southern California,Ming Hsieh Department of ECE,Los Angeles,CA,USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.42996869,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.6087999939918518,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.6087999939918518,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.20960000157356262,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.053700000047683716,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6348999738693237},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5738999843597412},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5254999995231628},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.49309998750686646},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.47369998693466187},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4047999978065491},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.3970000147819519},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3596000075340271}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7351999878883362},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6348999738693237},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5738999843597412},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5254999995231628},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.49309998750686646},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.47369998693466187},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4047999978065491},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.3970000147819519},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3596000075340271},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.35199999809265137},{"id":"https://openalex.org/C2777403171","wikidata":"https://www.wikidata.org/wiki/Q7578732","display_name":"Splitter","level":2,"score":0.3463999927043915},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.31619998812675476},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.314300000667572},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.31130000948905945},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3034999966621399},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.29980000853538513},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.29649999737739563},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.2879999876022339},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.2709999978542328},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.2653999924659729},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2506999969482422}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240800","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240800","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1576295179","https://openalex.org/W1969428739","https://openalex.org/W2060108852","https://openalex.org/W2070992435","https://openalex.org/W2087656024","https://openalex.org/W2098428470","https://openalex.org/W2112173236","https://openalex.org/W2135250302","https://openalex.org/W2160252016","https://openalex.org/W2247668026","https://openalex.org/W2595507424","https://openalex.org/W2761225910","https://openalex.org/W2902765665","https://openalex.org/W2913835504","https://openalex.org/W2990578448","https://openalex.org/W4205992448","https://openalex.org/W4234887147","https://openalex.org/W4280523317","https://openalex.org/W4312648309","https://openalex.org/W4320713391","https://openalex.org/W4385975642","https://openalex.org/W4388893858","https://openalex.org/W4393146427","https://openalex.org/W4393146741","https://openalex.org/W4394598493","https://openalex.org/W4394806911","https://openalex.org/W4401203353","https://openalex.org/W4401567948","https://openalex.org/W4402835805","https://openalex.org/W4406014654"],"related_works":[],"abstract_inverted_index":{"Single":[0],"Flux":[1],"Quantum":[2],"(SFQ)":[3],"digital":[4],"logic":[5],"offers":[6],"a":[7,55,104,127,149],"promising":[8],"path":[9,27,66],"to":[10,20,37,117,132],"energy-efficient,":[11],"high-performance":[12],"computing,":[13],"but":[14],"faces":[15],"significant":[16],"scalability":[17],"challenges\u2013particularly":[18],"due":[19],"the":[21,30],"area":[22,98,119,143,159],"overhead":[23,40,101],"associated":[24],"with":[25],"gate-level":[26],"balancing":[28,67],"and":[29,61,69,86,93,99,120,144,160,164],"pipelining":[31],"of":[32],"splitter":[33,94],"trees.":[34],"Prior":[35],"efforts":[36],"reduce":[38],"this":[39],"often":[41],"unnecessarily":[42],"compromise":[43],"throughput,":[44],"diminishing":[45],"SFQ\u2019s":[46],"key":[47],"performance":[48,106,152],"advantage.":[49],"To":[50],"mitigate":[51],"this,":[52],"we":[53,139],"propose":[54],"timing-aware":[56,112,155],"optimization":[57],"framework":[58],"that":[59],"unifies":[60],"enhances":[62],"both":[63],"traditional":[64],"full":[65],"(FPB)":[68],"multi-phase":[70,134],"clocking":[71,114,157],"approaches.":[72],"Inspired":[73],"by":[74,162],"timing-driven":[75],"EDA":[76],"strategies":[77],"in":[78],"CMOS,":[79],"our":[80,111,154],"approach":[81],"explicitly":[82],"models":[83],"gate":[84],"delays":[85],"jointly":[87],"optimizes":[88],"clock":[89,129],"phase":[90],"assignments,":[91],"pipelining,":[92],"tree":[95],"construction,":[96],"minimizing":[97],"latency":[100,122,161],"while":[102],"achieving":[103],"given":[105],"target.":[107],"On":[108],"benchmark":[109],"circuits,":[110],"2-phase":[113],"achieves":[115],"up":[116],"30%":[118],"29%":[121],"reductions":[123],"over":[124],"FPB":[125],"at":[126,137],"27ps":[128],"period.":[130],"Compared":[131],"prior":[133],"methods":[135],"operating":[136],"42ps,":[138],"achieve":[140],"22%":[141],"lower":[142,146],"23%":[145],"latency.":[147],"At":[148],"tighter":[150],"21ps":[151],"target,":[153],"single-phase":[156],"improves":[158],"28%":[163],"7%,":[165],"respectively.":[166],"All":[167],"optimizations":[168],"are":[169],"implemented":[170],"using":[171],"scalable,":[172],"polynomial-time":[173],"algorithms.":[174]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-11-20T00:00:00"}
