{"id":"https://openalex.org/W7106138957","doi":"https://doi.org/10.1109/iccad66269.2025.11240773","title":"GradMap: A Gradient-Descent Approach to Simultaneous Technology Mapping, Buffer Insertion, and Gate Sizing","display_name":"GradMap: A Gradient-Descent Approach to Simultaneous Technology Mapping, Buffer Insertion, and Gate Sizing","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W7106138957","doi":"https://doi.org/10.1109/iccad66269.2025.11240773"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240773","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240773","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Hsin-Ying Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hsin-Ying Tsai","raw_affiliation_strings":["National Taiwan University,Graduate Institute of Electronics Engineering"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate Institute of Electronics Engineering","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Chung-Kai Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chung-Kai Wu","raw_affiliation_strings":["National Taiwan University,Graduate Institute of Electronics Engineering"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate Institute of Electronics Engineering","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Chih-Cheng Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Cheng Hsu","raw_affiliation_strings":["National Taiwan University,Graduate Institute of Electronics Engineering"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate Institute of Electronics Engineering","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":null,"display_name":"Jie-Hong R. Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jie-Hong R. Jiang","raw_affiliation_strings":["National Taiwan University,Graduate Institute of Electronics Engineering"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate Institute of Electronics Engineering","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.51176402,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6777999997138977,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6777999997138977,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.19249999523162842,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.05350000038743019,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.6100000143051147},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4973999857902527},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4542999863624573},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.4343999922275543},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.41909998655319214},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41760000586509705},{"id":"https://openalex.org/keywords/buffer","display_name":"Buffer (optical fiber)","score":0.382099986076355},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.3799999952316284},{"id":"https://openalex.org/keywords/parallelizable-manifold","display_name":"Parallelizable manifold","score":0.3792000114917755},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3490999937057495}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6586999893188477},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.6100000143051147},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4973999857902527},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4542999863624573},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4343999922275543},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.41909998655319214},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41760000586509705},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3952000141143799},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.382099986076355},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.3799999952316284},{"id":"https://openalex.org/C148047603","wikidata":"https://www.wikidata.org/wiki/Q1014612","display_name":"Parallelizable manifold","level":2,"score":0.3792000114917755},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3490999937057495},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3474000096321106},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.3467000126838684},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.3452000021934509},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34450000524520874},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.33719998598098755},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.33709999918937683},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.3366999924182892},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3328999876976013},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.33219999074935913},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.33059999346733093},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.31690001487731934},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.3151000142097473},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.31029999256134033},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30979999899864197},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.30630001425743103},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.3046000003814697},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3043999969959259},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.3005000054836273},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.2973000109195709},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29589998722076416},{"id":"https://openalex.org/C137836250","wikidata":"https://www.wikidata.org/wiki/Q984063","display_name":"Optimization problem","level":2,"score":0.28529998660087585},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.2777000069618225},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2757999897003174},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2676999866962433},{"id":"https://openalex.org/C134448949","wikidata":"https://www.wikidata.org/wiki/Q1384274","display_name":"Expediting","level":2,"score":0.2646999955177307},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.26269999146461487},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.25099998712539673},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.2508000135421753}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240773","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240773","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320331164","display_name":"National Science and Technology Council","ror":"https://ror.org/00wnb9798"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2007701500","https://openalex.org/W2100465945","https://openalex.org/W2346205343","https://openalex.org/W3212743974","https://openalex.org/W4212945444","https://openalex.org/W4239323126","https://openalex.org/W4241530675","https://openalex.org/W4293024026","https://openalex.org/W4389166825","https://openalex.org/W4390097745","https://openalex.org/W4405936061","https://openalex.org/W4409282378","https://openalex.org/W4409282463"],"related_works":[],"abstract_inverted_index":{"Technology":[0],"mapping":[1,21,56],"is":[2,143],"an":[3,101],"essential":[4],"step":[5],"bridging":[6],"logic":[7],"synthesis":[8],"and":[9,29,44,82,113],"physical":[10],"design":[11,15],"in":[12,106,110,115],"the":[13,34,97,120,128,137,154],"electronic":[14],"automation":[16],"(EDA)":[17],"flow.":[18],"However,":[19],"technology":[20,55,86,122],"algorithms":[22],"often":[23],"assume":[24],"a":[25,37,53,60,68,89,150],"simplified":[26],"delay":[27,70,74],"model":[28,71],"may":[30],"not":[31],"faithfully":[32],"optimize":[33],"circuit":[35],"under":[36],"realistic":[38],"cost":[39],"function":[40],"involving":[41],"area,":[42],"delay,":[43],"power":[45],"objectives.":[46],"In":[47],"this":[48],"work,":[49],"we":[50],"introduce":[51],"GradMap,":[52],"gradient-descent-based":[54],"framework":[57],"that":[58,96,126],"integrates":[59],"differentiable":[61],"static":[62],"timing":[63],"analysis":[64],"(STA)":[65],"engine":[66],"with":[67,146],"linear":[69],"for":[72],"accurate":[73],"estimation.":[75],"Additionally,":[76],"it":[77,142],"enables":[78],"simultaneous":[79],"buffer":[80],"insertion":[81],"gate":[83],"sizing":[84],"during":[85],"mapping,":[87],"providing":[88],"holistic":[90],"optimization":[91,117,162],"solution.":[92],"Experimental":[93],"results":[94],"show":[95],"new":[98],"method":[99,130],"achieves":[100],"average":[102],"improvement":[103],"of":[104],"7%":[105],"area-driven":[107],"optimization,":[108,112],"33%":[109],"delay-driven":[111],"25%":[114],"area-delay-product":[116],"compared":[118,135],"to":[119,136,153],"ABC":[121,140],"mapper.":[123],"We":[124],"note":[125],"although":[127],"gradient-descent":[129],"has":[131],"significant":[132],"runtime":[133],"overhead":[134],"highly":[138,144],"efficient":[139],"mapper,":[141],"parallelizable":[145],"GPU":[147],"acceleration":[148],"(in":[149],"way":[151],"similar":[152],"neural":[155],"network":[156],"training":[157],"process),":[158],"besides":[159],"attaining":[160],"high":[161],"quality":[163],"far":[164],"beyond":[165],"ABC\u2019s":[166],"ability.":[167]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-11-20T00:00:00"}
