{"id":"https://openalex.org/W7106159705","doi":"https://doi.org/10.1109/iccad66269.2025.11240752","title":"VeriSAT: the Hardware Design of Modern SAT Solver","display_name":"VeriSAT: the Hardware Design of Modern SAT Solver","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W7106159705","doi":"https://doi.org/10.1109/iccad66269.2025.11240752"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Yue Tao","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128818","display_name":"Institute of Software","ror":"https://ror.org/033dfsn42","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210128818"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yue Tao","raw_affiliation_strings":["Chinese Academy of Sciences,Key Laboratory of System Software, Institute of Software"],"affiliations":[{"raw_affiliation_string":"Chinese Academy of Sciences,Key Laboratory of System Software, Institute of Software","institution_ids":["https://openalex.org/I4210128818"]}]},{"author_position":"last","author":{"id":null,"display_name":"Shaowei Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128818","display_name":"Institute of Software","ror":"https://ror.org/033dfsn42","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210128818"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaowei Cai","raw_affiliation_strings":["Chinese Academy of Sciences,Key Laboratory of System Software, Institute of Software"],"affiliations":[{"raw_affiliation_string":"Chinese Academy of Sciences,Key Laboratory of System Software, Institute of Software","institution_ids":["https://openalex.org/I4210128818"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210128818"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.5996436,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11596","display_name":"Constraint Satisfaction and Optimization","score":0.5455999970436096,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11596","display_name":"Constraint Satisfaction and Optimization","score":0.5455999970436096,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.2824000120162964,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.09369999915361404,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6287999749183655},{"id":"https://openalex.org/keywords/benchmarking","display_name":"Benchmarking","score":0.6096000075340271},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5770999789237976},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5526000261306763},{"id":"https://openalex.org/keywords/tree-traversal","display_name":"Tree traversal","score":0.4900999963283539},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4381999969482422},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.4345000088214874},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.39559999108314514},{"id":"https://openalex.org/keywords/data-structure","display_name":"Data structure","score":0.3797999918460846}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8428000211715698},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6287999749183655},{"id":"https://openalex.org/C86251818","wikidata":"https://www.wikidata.org/wiki/Q816754","display_name":"Benchmarking","level":2,"score":0.6096000075340271},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5770999789237976},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5728999972343445},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5681999921798706},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5526000261306763},{"id":"https://openalex.org/C140745168","wikidata":"https://www.wikidata.org/wiki/Q1210082","display_name":"Tree traversal","level":2,"score":0.4900999963283539},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4381999969482422},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.4345000088214874},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.39559999108314514},{"id":"https://openalex.org/C162319229","wikidata":"https://www.wikidata.org/wiki/Q175263","display_name":"Data structure","level":2,"score":0.3797999918460846},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.3790999948978424},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3476000130176544},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.3391999900341034},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.32690000534057617},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3260999917984009},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.31850001215934753},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.3149999976158142},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.29660001397132874},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.2883000075817108},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.28679999709129333},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.28380000591278076},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.2791000008583069},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.2782999873161316},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.2759999930858612},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.2694999873638153},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2563000023365021},{"id":"https://openalex.org/C2776834041","wikidata":"https://www.wikidata.org/wiki/Q25346349","display_name":"Execution model","level":2,"score":0.2533000111579895},{"id":"https://openalex.org/C2781039887","wikidata":"https://www.wikidata.org/wiki/Q1391724","display_name":"Factor (programming language)","level":2,"score":0.2517000138759613}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1530851447","https://openalex.org/W1819209966","https://openalex.org/W1946319015","https://openalex.org/W1964010760","https://openalex.org/W1968898611","https://openalex.org/W1979411114","https://openalex.org/W2002276854","https://openalex.org/W2036265926","https://openalex.org/W2062897452","https://openalex.org/W2069523538","https://openalex.org/W2087446885","https://openalex.org/W2097169831","https://openalex.org/W2122601020","https://openalex.org/W2135613306","https://openalex.org/W2142785340","https://openalex.org/W2549680053","https://openalex.org/W2566535251","https://openalex.org/W2587833204","https://openalex.org/W2738419859","https://openalex.org/W2743942298","https://openalex.org/W2785837881","https://openalex.org/W2913257024","https://openalex.org/W2980174590","https://openalex.org/W2981823863","https://openalex.org/W2992368780","https://openalex.org/W3128313128","https://openalex.org/W3193251185","https://openalex.org/W4212839743","https://openalex.org/W4236423066","https://openalex.org/W4291657085","https://openalex.org/W4389166662","https://openalex.org/W4401834257","https://openalex.org/W4407360722","https://openalex.org/W4407953507"],"related_works":[],"abstract_inverted_index":{"VeriSAT":[0,44,108,132],"is":[1,123],"the":[2,21,138,147,172,183],"first":[3],"modern":[4],"SAT":[5,40,160,179],"solver":[6,142],"implemented":[7],"entirely":[8],"in":[9,75,158,177,190],"synthesizable":[10],"SystemVerilog,":[11],"leveraging":[12],"FPGA":[13],"architecture":[14,58],"for":[15,42,86,143,174,185],"hardware":[16],"acceleration.":[17],"This":[18,169],"paper":[19],"introduces":[20,45],"design":[22,151],"of":[23,120,149],"VeriSAT,":[24],"focusing":[25],"on":[26,127],"hardware-specific":[27],"optimizations":[28],"that":[29,107],"significantly":[30],"improve":[31],"performance":[32],"over":[33,137],"traditional":[34],"software-based":[35],"solvers.":[36],"By":[37],"rethinking":[38],"key":[39],"components":[41],"hardware,":[43],"custom":[46],"data":[47,61],"structures":[48],"and":[49,115,122,181,193],"parallelized":[50],"processes":[51],"to":[52,56],"accelerate":[53],"solving":[54],"efficiency.Central":[55],"VeriSAT's":[57],"are":[59],"hardware-optimized":[60],"structures.":[62],"A":[63],"linked-list":[64],"based":[65],"literal-watching":[66],"mechanism,":[67],"enhanced":[68],"with":[69],"cached":[70],"watching":[71],"literals,":[72],"reduces":[73],"latency":[74],"unit":[76],"propagation.":[77],"Additionally,":[78,131],"a":[79,118,134,154],"concurrent":[80],"propagation":[81],"tree":[82],"enables":[83],"simultaneous":[84],"traversal":[85],"faster":[87],"conflict":[88,100],"detection.":[89],"The":[90],"solver's":[91],"pipelined":[92],"clause":[93],"learning":[94],"further":[95],"boosts":[96],"throughput,":[97],"allowing":[98],"rapid":[99],"analysis":[101],"without":[102],"compromising":[103],"performance.Extensive":[104],"benchmarking":[105],"demonstrates":[106],"outperforms":[109],"two":[110],"other":[111],"FPGA-based":[112,159],"solvers,":[113],"SAT-Hard":[114],"SAT-Accel,":[116],"by":[117],"factor":[119],"1044x":[121],"18x":[124],"faster,":[125],"respectively,":[126],"curated":[128],"benchmark":[129],"instances.":[130],"shows":[133],"30x":[135],"speedup":[136],"popular":[139],"CPU-based":[140],"MiniSat":[141],"specific":[144],"datasets,":[145],"validating":[146],"effectiveness":[148],"our":[150],"optimizations.VeriSAT":[152],"represents":[153],"significant":[155],"leap":[156],"forward":[157],"solving,":[161],"offering":[162],"unprecedented":[163],"efficiency":[164],"through":[165],"its":[166],"hardware-tailored":[167],"design.":[168],"work":[170],"lays":[171],"foundation":[173],"future":[175],"advancements":[176],"hardware-accelerated":[178],"solvers":[180],"paves":[182],"way":[184],"more":[186],"scalable,":[187],"high-performance":[188],"solutions":[189],"both":[191],"academic":[192],"industrial":[194],"applications.":[195]},"counts_by_year":[],"updated_date":"2025-11-23T05:10:03.516525","created_date":"2025-11-20T00:00:00"}
