{"id":"https://openalex.org/W4416429976","doi":"https://doi.org/10.1109/iccad66269.2025.11240694","title":"GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection","display_name":"GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416429976","doi":"https://doi.org/10.1109/iccad66269.2025.11240694"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240694","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240694","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027776770","display_name":"Chunyuan Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chunyuan Zhao","raw_affiliation_strings":["Peking University,School of Integrated Circuits,Beijing,China"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100639356","display_name":"Jiarui Wang","orcid":"https://orcid.org/0000-0002-7054-384X"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiarui Wang","raw_affiliation_strings":["Peking University,School of Integrated Circuits,Beijing,China"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089089524","display_name":"Xun Jiang","orcid":"https://orcid.org/0000-0001-5062-969X"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xun Jiang","raw_affiliation_strings":["Peking University,School of Integrated Circuits,Beijing,China"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012975828","display_name":"Jincheng Lou","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jincheng Lou","raw_affiliation_strings":["Peking University,School of Integrated Circuits,Beijing,China"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000933188","display_name":"Yibo Lin","orcid":"https://orcid.org/0000-0002-0977-2774"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yibo Lin","raw_affiliation_strings":["Peking University,School of Integrated Circuits,Beijing,China"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits,Beijing,China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5027776770"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":2.4442,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.91440347,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.4634000062942505,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.4634000062942505,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.26409998536109924,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.1873999983072281,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.636900007724762},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6227999925613403},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6226999759674072},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5724999904632568},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.519599974155426},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5002999901771545},{"id":"https://openalex.org/keywords/track","display_name":"Track (disk drive)","score":0.44179999828338623},{"id":"https://openalex.org/keywords/routing-table","display_name":"Routing table","score":0.438400000333786}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7224000096321106},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.636900007724762},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6227999925613403},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6226999759674072},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5724999904632568},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.519599974155426},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5002999901771545},{"id":"https://openalex.org/C89992363","wikidata":"https://www.wikidata.org/wiki/Q5961558","display_name":"Track (disk drive)","level":2,"score":0.44179999828338623},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.438400000333786},{"id":"https://openalex.org/C100776233","wikidata":"https://www.wikidata.org/wiki/Q2532492","display_name":"Bridge (graph theory)","level":2,"score":0.43779999017715454},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.3700000047683716},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.3571999967098236},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35659998655319214},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3287000060081482},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3025999963283539},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.29809999465942383},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.29409998655319214},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2921000123023987},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.28780001401901245},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2809999883174896},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26669999957084656},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.26499998569488525},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.2619999945163727},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.25290000438690186}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240694","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240694","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W2020097559","https://openalex.org/W2053902150","https://openalex.org/W2118269922","https://openalex.org/W2138938873","https://openalex.org/W2151690061","https://openalex.org/W2154308245","https://openalex.org/W2293811830","https://openalex.org/W2587992051","https://openalex.org/W2624895414","https://openalex.org/W2793662773","https://openalex.org/W2884307971","https://openalex.org/W2938881465","https://openalex.org/W2946549126","https://openalex.org/W3036410182","https://openalex.org/W3036696276","https://openalex.org/W3145272032","https://openalex.org/W3160984420","https://openalex.org/W4200128939","https://openalex.org/W4213332166","https://openalex.org/W4229539033","https://openalex.org/W4232904085","https://openalex.org/W4244849466","https://openalex.org/W4247156909","https://openalex.org/W4249660316","https://openalex.org/W4255326129","https://openalex.org/W4285232152","https://openalex.org/W4293024130","https://openalex.org/W4308575576","https://openalex.org/W4312121154","https://openalex.org/W4312759470","https://openalex.org/W4400230988","https://openalex.org/W4408395358","https://openalex.org/W4409282334","https://openalex.org/W4409282378"],"related_works":[],"abstract_inverted_index":{"Routing":[0],"remains":[1],"one":[2],"of":[3,57],"the":[4,115,142],"most":[5],"computationally":[6],"intensive":[7],"stages":[8],"in":[9,151],"VLSI":[10,153],"physical":[11],"design.":[12],"Track":[13],"assignment":[14,52,101],"serves":[15],"as":[16],"a":[17,97],"critical":[18],"bridge":[19],"between":[20,144],"global":[21],"routing":[22,26,135],"(GR)":[23],"and":[24,70,91,124,147],"detailed":[25,75,117,134],"(DR),":[27],"offering":[28],"more":[29],"accurate":[30,67],"routability":[31],"estimation":[32],"than":[33],"GR":[34],"while":[35,131],"providing":[36],"an":[37],"initial":[38,72],"solution":[39,73],"for":[40,74,83],"DR.":[41],"However,":[42],"existing":[43],"approaches":[44],"exhibit":[45],"two":[46],"key":[47],"limitations:":[48],"(1)":[49],"Most":[50],"track":[51,100],"methods":[53],"are":[54,63,80],"not":[55],"aware":[56],"design":[58,107,148],"rules,":[59],"which":[60,86],"makes":[61],"they":[62],"unable":[64],"to":[65,88],"provide":[66],"congestion":[68],"analysis":[69],"high-quality":[71],"routing.":[76,154],"(2)":[77],"Current":[78],"algorithms":[79],"exclusively":[81],"designed":[82],"CPU":[84],"architectures,":[85],"leads":[87],"limited":[89],"parallelism":[90],"long":[92],"runtime.":[93],"This":[94],"paper":[95],"presents":[96],"novel":[98],"GPU-accelerated":[99],"framework":[102,139],"that":[103],"holistically":[104],"addresses":[105],"these":[106],"rules.":[108],"Our":[109],"implementation":[110],"demonstrates":[111],"significant":[112],"improvements":[113],"over":[114],"state-of-the-art":[116],"router":[118],"TritonRoute-WXL,":[119],"achieving":[120],"20\u00d7":[121],"faster":[122],"runtime":[123],"25%":[125],"reduced":[126],"cpu":[127],"peak":[128],"memory":[129],"usage,":[130],"maintaining":[132],"competitive":[133],"quality.":[136],"The":[137],"proposed":[138],"effectively":[140],"bridges":[141],"gap":[143],"computational":[145],"efficiency":[146],"rule":[149],"awareness":[150],"modern":[152]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-03-12T08:34:05.389933","created_date":"2025-11-20T00:00:00"}