{"id":"https://openalex.org/W7106097711","doi":"https://doi.org/10.1109/iccad66269.2025.11240688","title":"DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCO","display_name":"DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCO","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W7106097711","doi":"https://doi.org/10.1109/iccad66269.2025.11240688"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Keyu Peng","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Keyu Peng","raw_affiliation_strings":["Southeast University,National ASIC System Engineering Center,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southeast University,National ASIC System Engineering Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yinuo Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yinuo Wu","raw_affiliation_strings":["Southeast University,National ASIC System Engineering Center,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southeast University,National ASIC System Engineering Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Zhengzhe Zheng","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhengzhe Zheng","raw_affiliation_strings":["Southeast University,National ASIC System Engineering Center,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southeast University,National ASIC System Engineering Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Hao Gu","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Gu","raw_affiliation_strings":["Southeast University,National ASIC System Engineering Center,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southeast University,National ASIC System Engineering Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ziran Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ziran Zhu","raw_affiliation_strings":["Southeast University,National ASIC System Engineering Center,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southeast University,National ASIC System Engineering Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Chao Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chao Wang","raw_affiliation_strings":["Southeast University,National ASIC System Engineering Center,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southeast University,National ASIC System Engineering Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"last","author":{"id":null,"display_name":"Jun Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Yang","raw_affiliation_strings":["Southeast University,National ASIC System Engineering Center,Nanjing,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Southeast University,National ASIC System Engineering Center,Nanjing,China","institution_ids":["https://openalex.org/I76569877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I76569877"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.0032999999821186066,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.002400000113993883,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.503600001335144},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.48240000009536743},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4812000095844269},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.4643999934196472},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.41119998693466187},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.3562999963760376},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.3098999857902527},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.30709999799728394},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2980000078678131}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.503600001335144},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.48240000009536743},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4812000095844269},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.4643999934196472},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45840001106262207},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.41119998693466187},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.3562999963760376},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3418000042438507},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3386000096797943},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3118000030517578},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.3098999857902527},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.30709999799728394},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3061000108718872},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2980000078678131},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29120001196861267},{"id":"https://openalex.org/C163716315","wikidata":"https://www.wikidata.org/wiki/Q901177","display_name":"Gaussian","level":2,"score":0.2904999852180481},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.2896000146865845},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.2888999879360199},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.28870001435279846},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.28619998693466187},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.2840999960899353},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.28189998865127563},{"id":"https://openalex.org/C184898388","wikidata":"https://www.wikidata.org/wiki/Q1435712","display_name":"Pairwise comparison","level":2,"score":0.27709999680519104},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.27649998664855957},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.27549999952316284},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2680000066757202},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.26759999990463257},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.26440000534057617},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.2614000141620636},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240688","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240688","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320324856","display_name":"Southeast University","ror":"https://ror.org/04ct4d772"},{"id":"https://openalex.org/F4320337504","display_name":"Research and Development","ror":"https://ror.org/027s68j25"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W602497127","https://openalex.org/W1985292881","https://openalex.org/W2009815534","https://openalex.org/W2020461489","https://openalex.org/W2022218016","https://openalex.org/W2043780523","https://openalex.org/W2773750423","https://openalex.org/W2945592068","https://openalex.org/W3091734033","https://openalex.org/W3100453629","https://openalex.org/W3174654674","https://openalex.org/W3211857759","https://openalex.org/W4200577934","https://openalex.org/W4223927598","https://openalex.org/W4253397218","https://openalex.org/W4353031993","https://openalex.org/W4387129402","https://openalex.org/W4393140659"],"related_works":[],"abstract_inverted_index":{"As":[0],"the":[1,12,36,87,104,113,148,184,189,198,224],"increasing":[2],"demands":[3],"of":[4,15,115,188,226],"design":[5,37,49,167,214],"technology":[6],"co-optimization":[7],"(DTCO)":[8],"in":[9,228],"advanced":[10],"nodes,":[11],"rigid":[13],"configurations":[14],"standard":[16],"cells":[17],"impose":[18],"significant":[19,205],"limitations":[20],"on":[21,35],"wirelength":[22,46,170,208],"and":[23,47,83,134,152,169,186,197,211,213,218],"area":[24,168,215],"optimization.":[25],"A":[26,175],"more":[27],"flexible":[28],"alternative":[29],"is":[30,144,179],"to":[31,66,80,96,119,146,165,182,193],"place":[32],"transistors":[33,85],"directly":[34],"canvas,":[38],"allowing":[39],"for":[40,128,232],"precise":[41],"transistor-level":[42,60,200,233],"adjustments":[43],"that":[44],"reduce":[45],"minimize":[48],"area.":[50],"In":[51],"this":[52],"paper,":[53],"we":[54,102,155],"propose":[55,103],"DiSPlace,":[56],"a":[57,137,157,194],"novel":[58],"diffusion-sharing-driven":[59,106],"placement":[61,75,108,163],"algorithm":[62,203],"beyond":[63],"standard-cell":[64],"boundaries":[65],"fully":[67],"leverage":[68],"DTCO.":[69],"We":[70],"first":[71,105],"present":[72],"an":[73,98,125],"in-cell":[74],"based":[76],"transistor":[77,121],"pairing":[78],"method":[79,164],"pair":[81],"PMOS":[82],"NMOS":[84],"with":[86,112,140],"same":[88],"gate":[89],"net,":[90],"followed":[91,123],"by":[92,124,209,216],"incorporating":[93],"Gaussian":[94],"perturbations":[95],"generate":[97],"initial":[99],"placement.":[100,174],"Then,":[101],"global":[107],"framework.":[109],"It":[110],"begins":[111],"construction":[114],"diffusion":[116,131],"sharing":[117],"nets":[118],"guide":[120],"placement,":[122],"analytical":[126,149],"model":[127,150],"simultaneously":[129],"optimizing":[130],"sharing,":[132],"wirelength,":[133],"density.":[135],"Besides,":[136],"nonlinear":[138],"optimization":[139],"adaptive":[141],"penalty":[142],"adjustment":[143],"presented":[145],"solve":[147],"effectively":[151],"efficiently.":[153],"Finally,":[154],"develop":[156],"satisfiability":[158],"modulo":[159],"theories":[160],"(SMT)-based":[161],"detailed":[162],"optimize":[166],"while":[171],"ensuring":[172],"legal":[173],"diffusion-sharing-aware":[176],"partitioning":[177],"technique":[178],"also":[180],"developed":[181],"enhance":[183],"scalability":[185],"efficiency":[187],"SMT-based":[190],"method.":[191],"Compared":[192],"standard-cell-based":[195],"placer":[196],"state-of-the-art":[199],"placer,":[201],"our":[202],"achieves":[204],"improvements,":[206],"reducing":[207],"18%":[210],"11%,":[212],"24%":[217],"4%,":[219],"respectively.":[220],"These":[221],"results":[222],"highlight":[223],"effectiveness":[225],"DiSPlace":[227],"achieving":[229],"high-quality":[230],"placements":[231],"designs.":[234]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-11-20T00:00:00"}