{"id":"https://openalex.org/W4416430018","doi":"https://doi.org/10.1109/iccad66269.2025.11240659","title":"Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems","display_name":"Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416430018","doi":"https://doi.org/10.1109/iccad66269.2025.11240659"},"language":"en","primary_location":{"id":"doi:10.1109/iccad66269.2025.11240659","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240659","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2508.03837","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016373122","display_name":"Davide Zoni","orcid":"https://orcid.org/0000-0002-9951-062X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Zoni","raw_affiliation_strings":["Informazione e Bioingegneria (DEIB),Dipartimento di Elettronica,Milano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informazione e Bioingegneria (DEIB),Dipartimento di Elettronica,Milano,Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012420168","display_name":"Andrea Galimberti","orcid":"https://orcid.org/0000-0003-0254-3933"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Galimberti","raw_affiliation_strings":["Informazione e Bioingegneria (DEIB),Dipartimento di Elettronica,Milano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informazione e Bioingegneria (DEIB),Dipartimento di Elettronica,Milano,Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114368847","display_name":"Adriano Guarisco","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Adriano Guarisco","raw_affiliation_strings":["Informazione e Bioingegneria (DEIB),Dipartimento di Elettronica,Milano,Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informazione e Bioingegneria (DEIB),Dipartimento di Elettronica,Milano,Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.89410001039505,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.89410001039505,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.053599998354911804,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.008200000040233135,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6581000089645386},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5806000232696533},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5412999987602234},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48420000076293945},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4754999876022339},{"id":"https://openalex.org/keywords/high-fidelity","display_name":"High fidelity","score":0.3441999852657318},{"id":"https://openalex.org/keywords/fidelity","display_name":"Fidelity","score":0.3237999975681305},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.2957000136375427}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7788000106811523},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6581000089645386},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5806000232696533},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5412999987602234},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5202999711036682},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5174999833106995},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48420000076293945},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4754999876022339},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37119999527931213},{"id":"https://openalex.org/C113364801","wikidata":"https://www.wikidata.org/wiki/Q26674","display_name":"High fidelity","level":2,"score":0.3441999852657318},{"id":"https://openalex.org/C2776459999","wikidata":"https://www.wikidata.org/wiki/Q2119376","display_name":"Fidelity","level":2,"score":0.3237999975681305},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2957000136375427},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2863999903202057},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.28049999475479126},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.2802000045776367},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.2802000045776367},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2700999975204468},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.2653999924659729},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.2630999982357025},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.26170000433921814},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.2556999921798706},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.2533000111579895},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.251800000667572}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240659","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240659","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:2508.03837","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2508.03837","pdf_url":"https://arxiv.org/pdf/2508.03837","source":{"id":"https://openalex.org/S4393918464","display_name":"ArXiv.org","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"pmh:doi:10.48550/arxiv.2508.03837","is_oa":true,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4406922384","display_name":"Open MIND","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"publisher-specific-oa","license_id":"https://openalex.org/licenses/publisher-specific-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"},{"id":"pmh:oai:re.public.polimi.it:11311/1298053","is_oa":false,"landing_page_url":"https://hdl.handle.net/11311/1298053","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2508.03837","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2508.03837","pdf_url":"https://arxiv.org/pdf/2508.03837","source":{"id":"https://openalex.org/S4393918464","display_name":"ArXiv.org","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W2027829345","https://openalex.org/W2034062945","https://openalex.org/W2074504559","https://openalex.org/W2137385009","https://openalex.org/W2147657366","https://openalex.org/W2150073849","https://openalex.org/W2417495832","https://openalex.org/W2528431790","https://openalex.org/W2762155252","https://openalex.org/W2884267664","https://openalex.org/W2950963990","https://openalex.org/W3027123178","https://openalex.org/W3027968530","https://openalex.org/W3032789745","https://openalex.org/W3081627712","https://openalex.org/W3203530736","https://openalex.org/W4249553981","https://openalex.org/W4251534053","https://openalex.org/W4364303238","https://openalex.org/W4366274287","https://openalex.org/W4389544721","https://openalex.org/W4390693436","https://openalex.org/W4400139036","https://openalex.org/W4401211850","https://openalex.org/W4403278162","https://openalex.org/W4406014479","https://openalex.org/W4406894610","https://openalex.org/W4408521164","https://openalex.org/W4411726620"],"related_works":[],"abstract_inverted_index":{"Designing":[0],"and":[1,30,69,91,97,120,167],"validating":[2],"efficient":[3],"cache-coherent":[4,35,175],"memory":[5,36,87,176],"subsystems":[6,88],"is":[7,22],"a":[8,23,129],"critical":[9],"yet":[10],"complex":[11],"task":[12],"in":[13,159,169],"the":[14,28,39,53,75],"development":[15,172],"of":[16,33,94,173],"modern":[17],"multi-core":[18],"system-on-chip":[19],"architectures.":[20],"Rhea":[21,42,56,82],"unified":[24],"framework":[25],"that":[26],"streamlines":[27],"design":[29,40,84],"system-level":[31],"validation":[32,54],"RTL":[34,47,60,77,86,148,174],"subsystems.":[37],"On":[38,52],"side,":[41,55],"generates":[43],"synthesizable,":[44],"highly":[45],"configurable":[46],"supporting":[48],"various":[49],"architectural":[50],"parameters.":[51],"integrates":[57],"Verilator\u2019s":[58],"cycle-accurate":[59],"simulation":[61,131],"with":[62,89,105,153],"gem5\u2019s":[63],"full-system":[64],"simulation,":[65],"allowing":[66],"realistic":[67],"workloads":[68],"operating":[70],"systems":[71],"to":[72,83,100,116,134,138,156],"run":[73],"alongside":[74],"actual":[76],"under":[78],"test.":[79],"We":[80],"apply":[81],"MSI-based":[85],"one":[90],"two":[92],"levels":[93],"private":[95],"caches":[96],"scaling":[98],"up":[99,133],"sixteen":[101],"cores.":[102],"Their":[103],"evaluation":[104],"22":[106],"applications":[107],"from":[108],"state-of-the-art":[109],"benchmark":[110],"suites":[111],"shows":[112],"intermediate":[113],"performance":[114],"relative":[115],"gem5":[117,139],"Ruby\u2019s":[118],"MI":[119],"MOESI":[121],"models.":[122],"The":[123],"hybrid":[124],"gem5-Verilator":[125],"co-simulation":[126],"flow":[127],"incurs":[128],"moderate":[130],"overhead,":[132],"2.7":[135],"times":[136,158],"compared":[137],"MI,":[140],"but":[141],"achieves":[142],"higher":[143],"fidelity":[144],"by":[145],"simulating":[146],"real":[147],"hardware.":[149],"This":[150],"overhead":[151],"decreases":[152],"scale,":[154],"down":[155],"1.6":[157],"sixteen-core":[160],"scenarios.":[161],"These":[162],"results":[163],"demonstrate":[164],"Rhea\u2019s":[165],"effectiveness":[166],"scalability":[168],"enabling":[170],"fast":[171],"subsystem":[177],"designs.":[178]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2025-10-10T00:00:00"}
