{"id":"https://openalex.org/W4416430011","doi":"https://doi.org/10.1109/iccad66269.2025.11240639","title":"Diffusion-Model-Enhanced Layout Pattern Generation for Sub-3nm DFM","display_name":"Diffusion-Model-Enhanced Layout Pattern Generation for Sub-3nm DFM","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W4416430011","doi":"https://doi.org/10.1109/iccad66269.2025.11240639"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240639","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240639","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023351465","display_name":"G.-S. Zhou","orcid":"https://orcid.org/0000-0002-6840-7160"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Guanglei Zhou","raw_affiliation_strings":["Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028018784","display_name":"Chen-Chia Chang","orcid":"https://orcid.org/0000-0003-3115-0733"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chen-Chia Chang","raw_affiliation_strings":["Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Junyao Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Junyao Zhang","raw_affiliation_strings":["Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024467177","display_name":"Jingyu Pan","orcid":"https://orcid.org/0000-0002-7187-5205"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jingyu Pan","raw_affiliation_strings":["Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102868511","display_name":"Yiran Chen","orcid":"https://orcid.org/0009-0004-4668-4505"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yiran Chen","raw_affiliation_strings":["Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University,Department of Electrical &amp; Computer Engineering,Durham,USA","institution_ids":["https://openalex.org/I170897317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.30213348,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.8061000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.8061000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12224","display_name":"Nanofabrication and Lithography Techniques","score":0.03519999980926514,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.031199999153614044,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.8600000143051147},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5424000024795532},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5038999915122986},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5024999976158142},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4724999964237213},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.42250001430511475},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.4162999987602234},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.4138999879360199},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.4090000092983246},{"id":"https://openalex.org/keywords/usable","display_name":"USable","score":0.38100001215934753}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.8600000143051147},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5424000024795532},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5038999915122986},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5024999976158142},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4925999939441681},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4724999964237213},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.4440999925136566},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4426000118255615},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.42250001430511475},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.4162999987602234},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.4138999879360199},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.4090000092983246},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.40619999170303345},{"id":"https://openalex.org/C2780615836","wikidata":"https://www.wikidata.org/wiki/Q2471869","display_name":"USable","level":2,"score":0.38100001215934753},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.37929999828338623},{"id":"https://openalex.org/C155512373","wikidata":"https://www.wikidata.org/wiki/Q287450","display_name":"Residual","level":2,"score":0.37439998984336853},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.36340001225471497},{"id":"https://openalex.org/C11727466","wikidata":"https://www.wikidata.org/wiki/Q1628157","display_name":"Inpainting","level":3,"score":0.34459999203681946},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.3393999934196472},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3375999927520752},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2915000021457672},{"id":"https://openalex.org/C184408114","wikidata":"https://www.wikidata.org/wiki/Q1502022","display_name":"Generative Design","level":3,"score":0.2865000069141388},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.28600001335144043},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.2831999957561493},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.2721000015735626},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2703999876976013},{"id":"https://openalex.org/C55396564","wikidata":"https://www.wikidata.org/wiki/Q3084971","display_name":"Process design","level":3,"score":0.26820001006126404},{"id":"https://openalex.org/C2778588580","wikidata":"https://www.wikidata.org/wiki/Q6043060","display_name":"Integrated design","level":2,"score":0.2667999863624573},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.2614000141620636},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.2606000006198883},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.25769999623298645},{"id":"https://openalex.org/C108710744","wikidata":"https://www.wikidata.org/wiki/Q4134329","display_name":"Blanking","level":2,"score":0.25529998540878296},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.250900000333786},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.2502000033855438}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240639","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240639","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W2138558886","https://openalex.org/W2332219458","https://openalex.org/W2595751671","https://openalex.org/W2806976363","https://openalex.org/W2998417722","https://openalex.org/W3007628184","https://openalex.org/W3211857759","https://openalex.org/W4285548914","https://openalex.org/W4312121035","https://openalex.org/W4312497550","https://openalex.org/W4312933868","https://openalex.org/W4367307954","https://openalex.org/W4386763651","https://openalex.org/W4404133489","https://openalex.org/W4404133891","https://openalex.org/W4404411236","https://openalex.org/W4409655099","https://openalex.org/W4409655126","https://openalex.org/W4413122368","https://openalex.org/W4414198979","https://openalex.org/W4414199206"],"related_works":[],"abstract_inverted_index":{"Modern":[0],"VLSI":[1],"layout":[2,31,52,84],"pattern":[3,69,129],"generation":[4],"for":[5,7,67,136],"design":[6,23,92],"manufacturability":[8],"(DFM)":[9],"at":[10,123],"sub-3":[11],"nm":[12],"nodes":[13,125],"faces":[14],"two":[15],"challenges:":[16],"1)":[17],"the":[18,26,34,74],"rapid":[19],"evolution":[20],"of":[21,28,36,57,76],"intricate":[22],"rules;":[24],"2)":[25],"scarcity":[27],"high-quality,":[29],"rule-compliant":[30],"data":[32],"during":[33],"development":[35],"new":[37],"process":[38],"technologies.":[39],"To":[40],"address":[41],"these":[42],"challenges,":[43],"we":[44],"introduce":[45],"a":[46,55,77,97,118,132],"diffusion-based":[47],"framework":[48],"that":[49,86],"re-frames":[50],"complex":[51,88],"synthesis":[53],"as":[54],"sequence":[56],"template-guided":[58],"inpainting":[59],"tasks,":[60],"which":[61],"significantly":[62],"reduces":[63],"training":[64],"sample":[65],"requirements":[66],"legal":[68,114],"generation.":[70],"This":[71],"approach":[72,111],"leverages":[73],"knowledge":[75],"pre-trained":[78],"image":[79],"foundation":[80],"model":[81],"to":[82,102,117],"generate":[83],"variations":[85],"satisfy":[87],"2D":[89],"metal":[90],"interconnect":[91],"rule":[93,121],"constraints,":[94],"and":[95],"introduces":[96],"novel":[98],"template-based":[99],"denoising":[100],"scheme":[101],"eliminate":[103],"residual":[104],"noisy":[105],"pixels.":[106],"Through":[107],"few-shot":[108],"fine-tuning,":[109],"our":[110],"uniquely":[112],"produces":[113],"layouts":[115],"conforming":[116],"full":[119],"sign-off":[120],"deck":[122],"sub-3nm":[124],"while":[126],"delivering":[127],"superior":[128],"diversity,":[130],"offering":[131],"production-ready,":[133],"data-efficient":[134],"solution":[135],"next-generation":[137],"technology":[138],"node":[139],"development.":[140]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-11-20T00:00:00"}
