{"id":"https://openalex.org/W7106105631","doi":"https://doi.org/10.1109/iccad66269.2025.11240636","title":"IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows","display_name":"IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows","publication_year":2025,"publication_date":"2025-10-26","ids":{"openalex":"https://openalex.org/W7106105631","doi":"https://doi.org/10.1109/iccad66269.2025.11240636"},"language":null,"primary_location":{"id":"doi:10.1109/iccad66269.2025.11240636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Haichuan Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Haichuan Liu","raw_affiliation_strings":["Peking University,School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Zizheng Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zizheng Guo","raw_affiliation_strings":["Peking University,School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Runsheng Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Runsheng Wang","raw_affiliation_strings":["Peking University,School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":null,"display_name":"Yibo Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yibo Lin","raw_affiliation_strings":["Peking University,School of Integrated Circuits"],"affiliations":[{"raw_affiliation_string":"Peking University,School of Integrated Circuits","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.6973,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.78748968,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7178000211715698,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7178000211715698,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.12229999899864197,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.05689999833703041,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timer","display_name":"Timer","score":0.8407999873161316},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.722000002861023},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6668000221252441},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5490000247955322},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.40610000491142273},{"id":"https://openalex.org/keywords/iterative-method","display_name":"Iterative method","score":0.33980000019073486},{"id":"https://openalex.org/keywords/algorithm-design","display_name":"Algorithm design","score":0.3287000060081482},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.32420000433921814},{"id":"https://openalex.org/keywords/iterative-and-incremental-development","display_name":"Iterative and incremental development","score":0.3197999894618988}],"concepts":[{"id":"https://openalex.org/C2776633867","wikidata":"https://www.wikidata.org/wiki/Q186612","display_name":"Timer","level":3,"score":0.8407999873161316},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7595000267028809},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.722000002861023},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6668000221252441},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5490000247955322},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4431000053882599},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4194999933242798},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.40610000491142273},{"id":"https://openalex.org/C159694833","wikidata":"https://www.wikidata.org/wiki/Q2321565","display_name":"Iterative method","level":2,"score":0.33980000019073486},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.3287000060081482},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3269999921321869},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.32420000433921814},{"id":"https://openalex.org/C143587482","wikidata":"https://www.wikidata.org/wiki/Q1543216","display_name":"Iterative and incremental development","level":2,"score":0.3197999894618988},{"id":"https://openalex.org/C97686452","wikidata":"https://www.wikidata.org/wiki/Q7604153","display_name":"Static analysis","level":2,"score":0.3019999861717224},{"id":"https://openalex.org/C112972136","wikidata":"https://www.wikidata.org/wiki/Q7595718","display_name":"Stability (learning theory)","level":2,"score":0.30000001192092896},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.296999990940094},{"id":"https://openalex.org/C2776291640","wikidata":"https://www.wikidata.org/wiki/Q2912517","display_name":"Value (mathematics)","level":2,"score":0.29260000586509705},{"id":"https://openalex.org/C2779982483","wikidata":"https://www.wikidata.org/wiki/Q6094420","display_name":"Iterative refinement","level":2,"score":0.2824999988079071},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.28130000829696655},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.28049999475479126},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.2773999869823456},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.27619999647140503},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.26759999990463257},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.2574000060558319},{"id":"https://openalex.org/C2777131613","wikidata":"https://www.wikidata.org/wiki/Q18394147","display_name":"Retard","level":2,"score":0.2517000138759613},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.25119999051094055}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad66269.2025.11240636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad66269.2025.11240636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4149247705936432,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1480958225","https://openalex.org/W1970795504","https://openalex.org/W1984588379","https://openalex.org/W2043172580","https://openalex.org/W2111183063","https://openalex.org/W2123316553","https://openalex.org/W2154363431","https://openalex.org/W2160252016","https://openalex.org/W2206870785","https://openalex.org/W2248975694","https://openalex.org/W2397503904","https://openalex.org/W2576595683","https://openalex.org/W2949216549","https://openalex.org/W2963366311","https://openalex.org/W3041526861","https://openalex.org/W3111098492","https://openalex.org/W3141440412","https://openalex.org/W3188917597","https://openalex.org/W3211750799","https://openalex.org/W3212679119","https://openalex.org/W4200128939","https://openalex.org/W4200319213","https://openalex.org/W4232034417","https://openalex.org/W4232044093","https://openalex.org/W4237185564","https://openalex.org/W4242440486","https://openalex.org/W4252769808","https://openalex.org/W4376460962","https://openalex.org/W4380607252","https://openalex.org/W4401568604","https://openalex.org/W4404134028","https://openalex.org/W4409282527"],"related_works":[],"abstract_inverted_index":{"Static":[0],"timing":[1,83],"analysis":[2,31],"(STA)":[3],"plays":[4],"an":[5],"essential":[6],"role":[7],"in":[8],"VLSI":[9],"design":[10],"optimization.":[11],"While":[12],"CPU-based":[13],"incremental":[14,70,78,112],"STA":[15,71],"methods":[16],"reduce":[17],"computational":[18],"overhead":[19],"by":[20],"selectively":[21],"updating":[22],"affected":[23],"circuit":[24],"regions,":[25],"and":[26,77,88,106],"GPU-accelerated":[27,69],"engines":[28],"improve":[29],"full-circuit":[30],"throughput,":[32],"effectively":[33],"combining":[34],"these":[35],"approaches":[36],"has":[37],"remained":[38],"challenging.":[39],"Existing":[40],"solutions":[41],"offer":[42],"only":[43],"partial":[44],"incrementality,":[45],"either":[46],"switching":[47],"to":[48,100,108],"CPU":[49,111],"processing":[50],"for":[51,85,114],"small":[52],"modifications":[53],"or":[54],"handling":[55],"solely":[56],"delay":[57],"value":[58],"changes":[59],"without":[60],"supporting":[61],"structural":[62,89],"updates.":[63],"We":[64],"introduce":[65],"IncreGPUSTA,":[66],"a":[67],"novel":[68],"algorithm":[72],"with":[73],"dual-CSR":[74],"data":[75],"structures":[76],"levelization":[79],"that":[80],"efficiently":[81],"processes":[82],"updates":[84],"both":[86],"localized":[87],"modifications.":[90],"Experimental":[91],"results":[92],"on":[93],"industrial":[94],"benchmarks":[95],"demonstrate":[96],"speedups":[97],"of":[98],"up":[99,107],"3.06\u00d7":[101],"over":[102,110],"GPU":[103],"full":[104],"Timer":[105,113],"72.50\u00d7":[109],"million-scale":[115],"designs.":[116]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-11-20T00:00:00"}