{"id":"https://openalex.org/W4389159459","doi":"https://doi.org/10.1109/iccad57390.2023.10323975","title":"An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design","display_name":"An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design","publication_year":2023,"publication_date":"2023-10-28","ids":{"openalex":"https://openalex.org/W4389159459","doi":"https://doi.org/10.1109/iccad57390.2023.10323975"},"language":"en","primary_location":{"id":"doi:10.1109/iccad57390.2023.10323975","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad57390.2023.10323975","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080828363","display_name":"Ismail Bustany","orcid":"https://orcid.org/0000-0002-7099-1546"},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ismail Bustany","raw_affiliation_strings":["Advanced Micro Devices,San Jose,CA,USA","Advanced Micro Devices, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices,San Jose,CA,USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"Advanced Micro Devices, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210137977"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081853227","display_name":"Grigor Gasparyan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Grigor Gasparyan","raw_affiliation_strings":["Advanced Micro Devices,San Jose,CA,USA","Advanced Micro Devices, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices,San Jose,CA,USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"Advanced Micro Devices, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210137977"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073558386","display_name":"Andrew B. Kahng","orcid":"https://orcid.org/0000-0002-4490-5018"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew B. Kahng","raw_affiliation_strings":["University of California San Diego,La Jolla,CA,USA","University of California San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California San Diego,La Jolla,CA,USA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"University of California San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066131957","display_name":"Ioannis Koutis","orcid":"https://orcid.org/0000-0003-1535-3397"},"institutions":[{"id":"https://openalex.org/I118118575","display_name":"New Jersey Institute of Technology","ror":"https://ror.org/05e74xb87","country_code":"US","type":"education","lineage":["https://openalex.org/I118118575"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ioannis Koutis","raw_affiliation_strings":["New Jersey Institute of Technology,Newark,NJ,USA","New Jersey Institute of Technology, Newark, NJ, USA"],"affiliations":[{"raw_affiliation_string":"New Jersey Institute of Technology,Newark,NJ,USA","institution_ids":["https://openalex.org/I118118575"]},{"raw_affiliation_string":"New Jersey Institute of Technology, Newark, NJ, USA","institution_ids":["https://openalex.org/I118118575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063613522","display_name":"Bodhisatta Pramanik","orcid":"https://orcid.org/0009-0004-6014-1048"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bodhisatta Pramanik","raw_affiliation_strings":["University of California San Diego,La Jolla,CA,USA","University of California San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California San Diego,La Jolla,CA,USA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"University of California San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078035974","display_name":"Zhiang Wang","orcid":"https://orcid.org/0000-0002-6669-9702"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiang Wang","raw_affiliation_strings":["University of California San Diego,La Jolla,CA,USA","University of California San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California San Diego,La Jolla,CA,USA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"University of California San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5080828363"],"corresponding_institution_ids":["https://openalex.org/I4210137977"],"apc_list":null,"apc_paid":null,"fwci":3.1302,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.92349134,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8389357328414917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7659423351287842},{"id":"https://openalex.org/keywords/embedding","display_name":"Embedding","score":0.7128347754478455},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5783072710037231},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5661796927452087},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5388588309288025},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.46021902561187744},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.41802161931991577},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.41585299372673035},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41206660866737366},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.39114609360694885},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2806764543056488},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.262499064207077},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.20826730132102966},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1101016104221344}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8389357328414917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7659423351287842},{"id":"https://openalex.org/C41608201","wikidata":"https://www.wikidata.org/wiki/Q980509","display_name":"Embedding","level":2,"score":0.7128347754478455},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5783072710037231},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5661796927452087},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5388588309288025},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.46021902561187744},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.41802161931991577},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.41585299372673035},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41206660866737366},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39114609360694885},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2806764543056488},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.262499064207077},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.20826730132102966},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1101016104221344},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad57390.2023.10323975","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad57390.2023.10323975","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G7915672093","display_name":null,"funder_award_id":"CCF-2112665,CCF-2039863,CCF-1813374","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1584753249","https://openalex.org/W1791881893","https://openalex.org/W1976661117","https://openalex.org/W2007480409","https://openalex.org/W2015889898","https://openalex.org/W2025826438","https://openalex.org/W2078174680","https://openalex.org/W2097845952","https://openalex.org/W2100637119","https://openalex.org/W2112469261","https://openalex.org/W2118986737","https://openalex.org/W2127480108","https://openalex.org/W2130258689","https://openalex.org/W2148750424","https://openalex.org/W2164340799","https://openalex.org/W2179287581","https://openalex.org/W2244550955","https://openalex.org/W2963918469","https://openalex.org/W2973075260","https://openalex.org/W3117926508","https://openalex.org/W3150210954","https://openalex.org/W3171752851","https://openalex.org/W4200036442","https://openalex.org/W4226435553","https://openalex.org/W4243467301","https://openalex.org/W4255476700","https://openalex.org/W4312121098","https://openalex.org/W4318684556","https://openalex.org/W4353031982","https://openalex.org/W6685152751","https://openalex.org/W6850443166"],"related_works":["https://openalex.org/W2181385951","https://openalex.org/W2072989701","https://openalex.org/W1727049600","https://openalex.org/W1481897060","https://openalex.org/W2183812348","https://openalex.org/W1738647919","https://openalex.org/W3000179092","https://openalex.org/W2026822479","https://openalex.org/W1986774039","https://openalex.org/W2976181145"],"abstract_inverted_index":{"With":[0],"the":[1,55,108,126],"increasing":[2],"complexity":[3],"of":[4,39,95,128],"IC":[5],"products,":[6],"large-scale":[7],"designs":[8],"must":[9],"be":[10],"efficiently":[11],"partitioned":[12],"into":[13],"multiple":[14],"blocks,":[15],"tiles,":[16],"or":[17,37],"devices":[18],"for":[19,47,61],"concurrent":[20],"backend":[21],"place-and-route":[22],"(P&R)":[23],"implementation.":[24],"State-of-the-art":[25],"partitioners":[26],"focus":[27],"on":[28,99,130],"balanced":[29],"min-cut":[30,87],"without":[31],"considering":[32],"constraints":[33],"such":[34],"as":[35],"timing":[36,77],"heterogeneity":[38],"resource":[40],"types.":[41],"They":[42],"are":[43],"thus":[44],"increasingly":[45],"unsuitable":[46],"current":[48],"physical":[49,63],"design":[50],"requirements.":[51],"We":[52],"introduce":[53],"TritonPart,":[54],"first":[56],"open-source,":[57],"constraints-driven":[58],"partitioning":[59],"tool":[60],"VLSI":[62],"design.":[64],"TritonPart":[65,89,105,123],"employs":[66],"efficient":[67],"algorithms":[68],"to":[69,97,144],"handle":[70],"constraints,":[71],"including":[72],"multi-dimensional":[73],"balance,":[74],"embedding,":[75],"and":[76,114,133,146],"constraints.":[78],"Our":[79],"experimental":[80],"work":[81],"affirms":[82],"its":[83],"benefits.":[84],"For":[85,102,120],"standard":[86],"partitioning,":[88,104,122],"outperforms":[90],"hMETIS":[91,145],"[17],":[92],"with":[93],"improvements":[94],"up":[96],"~20%":[98],"some":[100],"benchmarks.":[101],"embedding-aware":[103],"effectively":[106],"leverages":[107],"embeddings":[109],"generated":[110],"by":[111,118],"SpecPart":[112],"[4]":[113],"improves":[115],"upon":[116],"it":[117],"~2%.":[119],"timing-aware":[121],"significantly":[124],"reduces":[125],"number":[127],"cuts":[129],"timing-critical":[131],"paths":[132,136],"prevents":[134],"timing-noncritical":[135],"from":[137],"becoming":[138],"critical":[139],"(~21X,":[140],"~119X":[141],"reduction":[142],"relative":[143],"KaHyPar":[147],"[31],":[148],"respectively).":[149]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":12},{"year":2023,"cited_by_count":2}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}
