{"id":"https://openalex.org/W4200016955","doi":"https://doi.org/10.1109/iccad51958.2021.9643546","title":"Banshee: A Fast LLVM-Based RISC-V Binary Translator","display_name":"Banshee: A Fast LLVM-Based RISC-V Binary Translator","publication_year":2021,"publication_date":"2021-11-01","ids":{"openalex":"https://openalex.org/W4200016955","doi":"https://doi.org/10.1109/iccad51958.2021.9643546"},"language":"en","primary_location":{"id":"doi:10.1109/iccad51958.2021.9643546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad51958.2021.9643546","pdf_url":null,"source":{"id":"https://openalex.org/S4363608354","display_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025031387","display_name":"Samuel Riedel","orcid":"https://orcid.org/0000-0002-5772-6377"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Samuel Riedel","raw_affiliation_strings":["IIS, ETH Zürich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIS, ETH Zürich","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024145677","display_name":"Fabian Schuiki","orcid":"https://orcid.org/0000-0002-9923-5031"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Fabian Schuiki","raw_affiliation_strings":["IIS, ETH Zürich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIS, ETH Zürich","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052998498","display_name":"Paul Scheffler","orcid":"https://orcid.org/0000-0003-4230-1381"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Paul Scheffler","raw_affiliation_strings":["IIS, ETH Zürich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIS, ETH Zürich","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058655278","display_name":"Florian Zaruba","orcid":"https://orcid.org/0000-0002-8194-6521"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Florian Zaruba","raw_affiliation_strings":["IIS, ETH Zürich"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIS, ETH Zürich","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["IIS, ETH Zürich","DEI, University of Bologna"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIS, ETH Zürich","institution_ids":[]},{"raw_affiliation_string":"DEI, University of Bologna","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.1968,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.87850467,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9006059169769287},{"id":"https://openalex.org/keywords/binary-translation","display_name":"Binary translation","score":0.7751936912536621},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.6967320442199707},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6739435791969299},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5420073866844177},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5205320119857788},{"id":"https://openalex.org/keywords/extensibility","display_name":"Extensibility","score":0.5150277614593506},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4641009569168091},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4422149360179901},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42723917961120605},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4257446527481079},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4133508801460266},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.39810454845428467},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3607025742530823},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.33594247698783875},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.2107580602169037}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9006059169769287},{"id":"https://openalex.org/C2778971978","wikidata":"https://www.wikidata.org/wiki/Q2287075","display_name":"Binary translation","level":3,"score":0.7751936912536621},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.6967320442199707},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6739435791969299},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5420073866844177},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5205320119857788},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.5150277614593506},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4641009569168091},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4422149360179901},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42723917961120605},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4257446527481079},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4133508801460266},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.39810454845428467},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3607025742530823},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.33594247698783875},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.2107580602169037},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccad51958.2021.9643546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad51958.2021.9643546","pdf_url":null,"source":{"id":"https://openalex.org/S4363608354","display_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/871088","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/871088","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1522250664","https://openalex.org/W1606621385","https://openalex.org/W2034062945","https://openalex.org/W2147657366","https://openalex.org/W2155612203","https://openalex.org/W2798598799","https://openalex.org/W2946072469","https://openalex.org/W2953955260","https://openalex.org/W3013692244","https://openalex.org/W3016309475","https://openalex.org/W3026967469","https://openalex.org/W3095022116","https://openalex.org/W3112773671","https://openalex.org/W3137426124","https://openalex.org/W3150538041","https://openalex.org/W3184107541","https://openalex.org/W3196886152","https://openalex.org/W4238274188","https://openalex.org/W4246166885","https://openalex.org/W6631155369","https://openalex.org/W6775816754","https://openalex.org/W6778206501","https://openalex.org/W6782864349","https://openalex.org/W6903938272"],"related_works":["https://openalex.org/W2538644970","https://openalex.org/W4376881175","https://openalex.org/W4310584696","https://openalex.org/W4385730960","https://openalex.org/W4237840813","https://openalex.org/W4364295250","https://openalex.org/W2128502296","https://openalex.org/W1983630549","https://openalex.org/W2993622674","https://openalex.org/W1833044483"],"abstract_inverted_index":{"System":[0],"simulators":[1],"are":[2,14],"essential":[3],"for":[4,16,187],"the":[5,68,94,104,132],"exploration,":[6],"evaluation,":[7],"and":[8,13,19,34,79,99,106,165,169,197],"verification":[9],"of":[10,64,108,134,141,177],"manycore":[11,162],"processors":[12],"vital":[15],"writing":[17],"software":[18],"developing":[20],"programming":[21],"models":[22,74],"in":[23,86],"conjunction":[24],"with":[25,62,116,137],"architecture":[26],"design.":[27],"A":[28],"promising":[29],"approach":[30],"to":[31,93,102,118,179],"fast,":[32],"scalable,":[33],"instruction-accurate":[35,47],"simulation":[36,175],"is":[37,91],"binary":[38,56,120],"translation.":[39],"In":[40],"this":[41],"paper,":[42],"we":[43],"present":[44],"Banshee,":[45],"an":[46,138],"full-system":[48],"RISC-V":[49,161,209],"multi-core":[50,199],"simulator":[51],"based":[52],"on":[53,157],"LLVM-powered":[54],"ahead-of-time":[55],"translation":[57,121],"that":[58],"can":[59],"simulate":[60],"systems":[61],"thousands":[63],"cores.":[65],"Banshee":[66,90,123,151],"supports":[67,124],"RV32IMAFD":[69],"instruction":[70],"set.":[71],"It":[72],"also":[73],"peripherals,":[75],"custom":[76,208],"ISA":[77,110,210],"extensions,":[78],"a":[80,113,128],"multi-level,":[81],"actively-managed":[82],"memory":[83],"hierarchy":[84],"used":[85],"existing":[87,119],"multi-cluster":[88],"systems.":[89],"agnostic":[92],"host":[95],"architecture,":[96],"fully":[97],"open-source,":[98],"easily":[100],"extensible":[101],"facilitate":[103],"exploration":[105],"evaluation":[107],"new":[109],"extensions.":[111,211],"As":[112],"key":[114],"novelty":[115],"respect":[117],"approaches,":[122],"performance":[125],"estimation":[126],"through":[127],"lightweight":[129],"extension,":[130],"modeling":[131],"effect":[133],"architectural":[135],"latencies":[136],"average":[139],"deviation":[140],"only":[142],"2":[143],"%":[144],"from":[145],"their":[146],"actual":[147],"impact.":[148],"We":[149,173,201],"evaluate":[150],"by":[152,205],"simulating":[153],"various":[154],"compute-intensive":[155],"workloads":[156],"two":[158],"large-scale":[159],"open-source":[160],"systems,":[163,189],"Manticore":[164],"MemPool":[166],"(with":[167],"4096":[168],"256":[170],"cores,":[171],"respectively).":[172],"achieve":[174],"speeds":[176],"up":[178],"618":[180],"MIPS":[181],"per":[182],"core":[183],"or":[184],"72":[185],"GIPS":[186],"complete":[188],"exhibiting":[190],"almost":[191],"perfect":[192],"scaling,":[193],"competitive":[194],"single-core":[195],"performance,":[196],"leading":[198],"performance.":[200],"demonstrate":[202],"Banshee's":[203],"extensibility":[204],"implementing":[206],"multiple":[207]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2021-12-31T00:00:00"}