{"id":"https://openalex.org/W4200388390","doi":"https://doi.org/10.1109/iccad51958.2021.9643499","title":"IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs","display_name":"IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs","publication_year":2021,"publication_date":"2021-11-01","ids":{"openalex":"https://openalex.org/W4200388390","doi":"https://doi.org/10.1109/iccad51958.2021.9643499"},"language":"en","primary_location":{"id":"doi:10.1109/iccad51958.2021.9643499","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad51958.2021.9643499","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050270997","display_name":"Nathaniel Pinckney","orcid":"https://orcid.org/0000-0001-6159-8964"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nathaniel Pinckney","raw_affiliation_strings":["NVIDIA,Austin,TX,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA,Austin,TX,USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045219356","display_name":"Rangharajan Venkatesan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rangharajan Venkatesan","raw_affiliation_strings":["NVIDIA,Santa Clara,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA,Santa Clara,CA,USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001800455","display_name":"Ben Keller","orcid":"https://orcid.org/0000-0002-8117-1412"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ben Keller","raw_affiliation_strings":["NVIDIA,Santa Clara,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA,Santa Clara,CA,USA","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010156116","display_name":"Brucek Khailany","orcid":"https://orcid.org/0000-0002-7584-3489"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brucek Khailany","raw_affiliation_strings":["NVIDIA,Austin,TX,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA,Austin,TX,USA","institution_ids":["https://openalex.org/I4210127875"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210127875"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18655207,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8662105798721313},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7101868391036987},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6474868059158325},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6359308362007141},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6263241767883301},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6221280097961426},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6044331192970276},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5564275979995728},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4647340774536133},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4519132077693939},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.30892375111579895}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8662105798721313},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7101868391036987},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6474868059158325},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6359308362007141},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6263241767883301},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6221280097961426},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6044331192970276},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5564275979995728},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4647340774536133},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4519132077693939},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.30892375111579895},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad51958.2021.9643499","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad51958.2021.9643499","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6650245637","display_name":null,"funder_award_id":"HR0011-18-3-0007","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1983394510","https://openalex.org/W1984520032","https://openalex.org/W2062819906","https://openalex.org/W2065742943","https://openalex.org/W2108598243","https://openalex.org/W2113615756","https://openalex.org/W2118231264","https://openalex.org/W2134354173","https://openalex.org/W2139984346","https://openalex.org/W2509453741","https://openalex.org/W2734326062","https://openalex.org/W2808932028","https://openalex.org/W2997929983","https://openalex.org/W2999356938","https://openalex.org/W3092300766","https://openalex.org/W3110910439","https://openalex.org/W6752900154"],"related_works":["https://openalex.org/W2548514518","https://openalex.org/W4234221021","https://openalex.org/W2119904701","https://openalex.org/W2119674509","https://openalex.org/W1603163876","https://openalex.org/W2975035977","https://openalex.org/W2269990635","https://openalex.org/W2133642747","https://openalex.org/W2026454041","https://openalex.org/W2533063779"],"abstract_inverted_index":{"High-level":[0],"synthesis":[1],"(HLS)":[2],"has":[3,51],"recently":[4],"been":[5,54],"used":[6,55,127,181],"to":[7,77,163],"improve":[8,22],"design":[9,24,40,82,151,193,222],"productivity":[10,25],"for":[11,56,61,96,121,145,174,187,211,224],"many":[12],"units":[13],"in":[14,80,101,203,214],"today's":[15,46],"complex":[16,48],"SoCs.":[17],"HLS":[18,50,185],"tools":[19,114],"and":[20,29,67,73,99,112,119,177,205,231],"flows":[21],"chip":[23],"by":[26,132,219],"enabling":[27],"prototyping":[28,98,131],"automated":[30],"implementation":[31,100],"of":[32,45,135],"RTL":[33,175,209],"from":[34],"a":[35,42,94,183,192,229,232],"single":[36],"codebase.":[37],"Although":[38],"interconnect":[39,65,97,117,136,141,189,213,227],"is":[41,63,126,171,195],"critical":[43],"part":[44],"highly":[47],"SoCs,":[49],"not":[52],"historically":[53],"SoC-level":[57],"interconnect.":[58],"One":[59],"reason":[60],"this":[62,86],"that":[64,115],"architecture":[66],"physical":[68],"floorplan":[69],"are":[70],"tightly":[71],"coupled,":[72],"can":[74,179,206],"be":[75,180],"difficult":[76],"estimate":[78],"early":[79,129],"the":[81,150,221],"process.":[83],"To":[84],"address":[85],"gap,":[87],"we":[88],"propose":[89],"IPA":[90,105,138,158,197,218],"(Interconnect":[91],"Prototyping":[92],"Assistant),":[93],"framework":[95,125],"HLS-based":[102],"SoC":[103,212],"flows.":[104],"includes":[106],"an":[107,225],"application":[108],"programming":[109],"interface":[110],"(API)":[111],"accompanying":[113],"automate":[116],"modeling":[118],"generation":[120,190],"SystemC-based":[122],"designs.":[123],"Our":[124],"during":[128],"architectural":[130,200],"abstracting":[133],"specifics":[134],"implementation.":[137],"then":[139],"generates":[140],"models,":[142],"including":[143],"interfaces,":[144],"SystemC":[146,169],"cycle-accurate":[147],"simulations.":[148],"If":[149],"requires":[152],"long":[153],"wires":[154],"between":[155],"communication":[156],"units,":[157],"automatically":[159],"inserts":[160],"retiming":[161],"stages":[162],"meet":[164],"clock":[165],"frequency":[166],"targets.":[167],"IPA's":[168],"code":[170],"fully":[172],"HLS-compatible":[173],"creation,":[176],"thus":[178],"within":[182],"full-chip":[184],"flow":[186],"pushbutton":[188],"once":[191],"point":[194],"selected.":[196],"provides":[198],"accurate":[199],"performance":[201],"feedback":[202],"minutes":[204],"generate":[207],"high-quality":[208],"implementations":[210],"hours.":[215],"We":[216],"demonstrate":[217],"exploring":[220],"space":[223],"on-chip":[226],"on":[228],"micro-benchmark":[230],"deep":[233],"learning":[234],"accelerator.":[235]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}