{"id":"https://openalex.org/W4200079663","doi":"https://doi.org/10.1109/iccad51958.2021.9643439","title":"Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies","display_name":"Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies","publication_year":2021,"publication_date":"2021-11-01","ids":{"openalex":"https://openalex.org/W4200079663","doi":"https://doi.org/10.1109/iccad51958.2021.9643439"},"language":"en","primary_location":{"id":"doi:10.1109/iccad51958.2021.9643439","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad51958.2021.9643439","pdf_url":null,"source":{"id":"https://openalex.org/S4363608354","display_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030840336","display_name":"Andreas Krinke","orcid":"https://orcid.org/0000-0001-7081-4104"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Andreas Krinke","raw_affiliation_strings":["Institute of Electromechanical and Electronic Design (IFTE)"],"affiliations":[{"raw_affiliation_string":"Institute of Electromechanical and Electronic Design (IFTE)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075349265","display_name":"Shubham Rai","orcid":"https://orcid.org/0000-0002-6522-5628"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Shubham Rai","raw_affiliation_strings":["Chair For Processor Design (CfAED), Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair For Processor Design (CfAED), Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"TU Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["Chair For Processor Design (CfAED), Technische Universit\u00e4t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair For Processor Design (CfAED), Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070654831","display_name":"Jens Lienig","orcid":"https://orcid.org/0000-0002-2140-4587"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jens Lienig","raw_affiliation_strings":["Institute of Electromechanical and Electronic Design (IFTE)"],"affiliations":[{"raw_affiliation_string":"Institute of Electromechanical and Electronic Design (IFTE)","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5030840336"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.731,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.83244261,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"39","issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.8833895921707153},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.7185834050178528},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6548932194709778},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6158775687217712},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5514451861381531},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5302215218544006},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5248289704322815},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4553963243961334},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.420840859413147},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3210029602050781},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30524006485939026},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2604038119316101},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23430466651916504},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14017924666404724},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07990175485610962}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8833895921707153},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.7185834050178528},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6548932194709778},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6158775687217712},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5514451861381531},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5302215218544006},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5248289704322815},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4553963243961334},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.420840859413147},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3210029602050781},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30524006485939026},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2604038119316101},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23430466651916504},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14017924666404724},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07990175485610962}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad51958.2021.9643439","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad51958.2021.9643439","pdf_url":null,"source":{"id":"https://openalex.org/S4363608354","display_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G821014536","display_name":null,"funder_award_id":"439891087","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":48,"referenced_works":["https://openalex.org/W216197876","https://openalex.org/W1483713538","https://openalex.org/W1524250393","https://openalex.org/W1528837436","https://openalex.org/W1776822698","https://openalex.org/W1969849133","https://openalex.org/W1972841535","https://openalex.org/W1977426672","https://openalex.org/W1988747400","https://openalex.org/W2001346321","https://openalex.org/W2028407134","https://openalex.org/W2055215434","https://openalex.org/W2066748541","https://openalex.org/W2085803561","https://openalex.org/W2095410905","https://openalex.org/W2104994832","https://openalex.org/W2110770862","https://openalex.org/W2117181658","https://openalex.org/W2135674775","https://openalex.org/W2156409449","https://openalex.org/W2162651880","https://openalex.org/W2166127884","https://openalex.org/W2242458479","https://openalex.org/W2322754293","https://openalex.org/W2348197687","https://openalex.org/W2384779455","https://openalex.org/W2468019634","https://openalex.org/W2546380096","https://openalex.org/W2563335932","https://openalex.org/W2587608034","https://openalex.org/W2607365186","https://openalex.org/W2798959258","https://openalex.org/W2799027281","https://openalex.org/W2799158414","https://openalex.org/W2906629987","https://openalex.org/W2977663466","https://openalex.org/W2981431027","https://openalex.org/W3036970922","https://openalex.org/W3099803115","https://openalex.org/W3107498708","https://openalex.org/W3136090073","https://openalex.org/W3185234608","https://openalex.org/W4236269389","https://openalex.org/W4288083501","https://openalex.org/W6642652938","https://openalex.org/W6643203157","https://openalex.org/W6674354551","https://openalex.org/W6729318695"],"related_works":["https://openalex.org/W1544665014","https://openalex.org/W2748364266","https://openalex.org/W4243861219","https://openalex.org/W2556374054","https://openalex.org/W2069545207","https://openalex.org/W2092579166","https://openalex.org/W2159103767","https://openalex.org/W2091330445","https://openalex.org/W2170979950","https://openalex.org/W1900707063"],"abstract_inverted_index":{"Recently":[0],"proposed":[1,133],"ambipolar":[2],"nanotechnologies":[3],"allow":[4],"the":[5,19,48,51,64,72,108],"development":[6],"of":[7,98,111,118,141],"reconfigurable":[8,37,99,109,120],"circuits":[9,31,56,90],"with":[10,91],"low":[11],"area":[12,140],"and":[13,114],"power":[14,124],"overheads":[15],"as":[16],"compared":[17,146],"to":[18,41,47,61,63,82,106,143,147],"conventional":[20,26,148],"CMOS":[21],"technology.":[22],"However,":[23],"using":[24,131],"a":[25,112,136],"physical":[27,52,85],"synthesis":[28,53,86],"flow":[29,54,87],"for":[30,55,88],"that":[32,50,80],"include":[33],"gates":[34],"based":[35,57],"on":[36,58],"FETs":[38],"(RFETs)":[39],"leads":[40],"sub-optimal":[42],"results.":[43],"This":[44],"is":[45],"due":[46],"fact":[49],"RFETs":[59],"has":[60],"cater":[62],"additional":[65],"gate":[66],"terminal":[67],"per":[68],"RFET":[69],"transistors.":[70],"In":[71],"present":[73],"work,":[74],"we":[75],"explore":[76],"three":[77],"important":[78],"verticals":[79],"lead":[81],"an":[83],"optimized":[84,96,116],"RFET-based":[89],"circuit-level":[92],"reconfigurability:":[93],"(1)":[94],"designing":[95],"layouts":[97],"gates,":[100],"(2)":[101],"utilize":[102],"special":[103],"driver":[104],"cells":[105],"drive":[107],"portions":[110],"circuit,":[113],"(3)":[115],"placement":[117],"these":[119],"parts":[121],"in":[122,138],"separate":[123],"domains.":[125],"Experimental":[126],"evaluations":[127],"over":[128],"EPFL":[129],"benchmarks":[130],"our":[132],"approach":[134],"show":[135],"reduction":[137],"chip":[139],"up":[142],"17.5%":[144],"when":[145],"flows.":[149]},"counts_by_year":[{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
