{"id":"https://openalex.org/W2996952402","doi":"https://doi.org/10.1109/iccad45719.2019.8942111","title":"A General Logic Synthesis Framework for Memristor-based Logic Design","display_name":"A General Logic Synthesis Framework for Memristor-based Logic Design","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W2996952402","doi":"https://doi.org/10.1109/iccad45719.2019.8942111","mag":"2996952402"},"language":"en","primary_location":{"id":"doi:10.1109/iccad45719.2019.8942111","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad45719.2019.8942111","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103138440","display_name":"Zhenhua Zhu","orcid":"https://orcid.org/0009-0007-9259-7180"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhenhua Zhu","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075614381","display_name":"Mingyuan Ma","orcid":"https://orcid.org/0009-0000-0541-5625"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingyuan Ma","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061759563","display_name":"Jialong Liu","orcid":"https://orcid.org/0000-0002-4303-3617"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jialong Liu","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112594373","display_name":"Liying Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liying Xu","raw_affiliation_strings":["Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100373745","display_name":"Xiaohong Chen","orcid":"https://orcid.org/0000-0002-9797-8384"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]},{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoming Chen","raw_affiliation_strings":["Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057584787","display_name":"Yuchao Yang","orcid":"https://orcid.org/0000-0003-4674-4059"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuchao Yang","raw_affiliation_strings":["Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100445148","display_name":"Yu Wang","orcid":"https://orcid.org/0000-0002-0597-3544"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu Wang","raw_affiliation_strings":["BNRist, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"BNRist, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023755254","display_name":"Huazhong Yang","orcid":"https://orcid.org/0000-0003-2421-353X"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huazhong Yang","raw_affiliation_strings":["BNRist, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"BNRist, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5103138440"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.5961,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.69917432,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7150615453720093},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6317595839500427},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6307262182235718},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5329839587211609},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5122300982475281},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.5102293491363525},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.47488731145858765},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24135860800743103},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1718439757823944},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08596143126487732}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7150615453720093},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6317595839500427},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6307262182235718},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5329839587211609},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5122300982475281},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.5102293491363525},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.47488731145858765},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24135860800743103},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1718439757823944},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08596143126487732}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad45719.2019.8942111","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad45719.2019.8942111","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2004782555","https://openalex.org/W2025674646","https://openalex.org/W2081729575","https://openalex.org/W2220698963","https://openalex.org/W2285660444","https://openalex.org/W2286699138","https://openalex.org/W2396622873","https://openalex.org/W2546945562","https://openalex.org/W2554218635","https://openalex.org/W2613967375","https://openalex.org/W2770634378","https://openalex.org/W2772943299","https://openalex.org/W2910707180"],"related_works":["https://openalex.org/W1553855433","https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2170504327","https://openalex.org/W2789349722","https://openalex.org/W2766377030","https://openalex.org/W1987454796","https://openalex.org/W2102927888"],"abstract_inverted_index":{"Memristor-based":[0],"logic":[1,33,43,51,71,81,86,109,120,139],"design":[2,150],"gives":[3],"an":[4],"alternative":[5],"solution":[6],"to":[7,133,156],"improve":[8],"the":[9,18,54,58,67,124,143,159,175,181,188,197,201,213,224],"energy":[10],"efficiency":[11],"of":[12,60,69,117,177],"computing":[13,21],"systems,":[14],"benefiting":[15],"from":[16],"combining":[17],"memory":[19,64,125],"with":[20,35,158,196,223],"units.":[22],"Inspired":[23],"by":[24,141],"this":[25,75],"thought,":[26],"previous":[27],"work":[28],"has":[29],"demonstrated":[30],"various":[31,115],"memristor-based":[32,85,119],"families":[34,121,140],"different":[36],"attributes":[37],"and":[38,57,101,104,122,138,191,210],"computation":[39,209],"patterns.":[40],"Besides,":[41],"some":[42],"synthesis":[44,72,82,103,110,153,161,183,194,203],"tools":[45,184],"are":[46],"designed":[47],"for":[48,84,94,114,208],"specific":[49],"memristive":[50,95,136],"implementations.":[52],"However,":[53],"poor":[55],"universality":[56],"neglect":[59],"realistic":[61],"constraints":[62],"in":[63],"largely":[65],"restrict":[66],"utility":[68],"these":[70],"tools.":[73],"In":[74],"paper,":[76],"we":[77,148],"propose":[78],"a":[79,89,97,102,151],"general":[80],"framework":[83,111,169],"design,":[87],"containing":[88],"universal":[90,144],"abstract":[91],"description":[92],"method":[93],"logic,":[96],"mapping":[98,105,172],"rules":[99],"generator,":[100],"flow.":[106],"The":[107],"proposed":[108,214],"is":[112,130,206],"suitable":[113],"types":[116],"existing":[118,182,202],"takes":[123],"status":[126],"into":[127],"consideration.":[128],"It":[129],"also":[131,149],"possible":[132],"handle":[134],"future":[135],"devices":[137],"providing":[142],"abstraction":[145],"interface.":[146],"Furthermore,":[147],"circuit-partitioning-based":[152],"acceleration":[154,215],"strategy":[155],"tackle":[157],"long":[160],"time":[162],"problem.":[163],"Experimental":[164],"results":[165,173,195],"show":[166],"that,":[167],"our":[168],"can":[170,217],"generate":[171],"under":[174,187],"restriction":[176],"limited":[178],"resource,":[179],"while":[180],"may":[185],"fail":[186],"same":[189,198],"restriction,":[190],"achieve":[192,218],"comparable":[193],"resource":[199],"as":[200],"tools,":[204],"which":[205],"enough":[207],"storage.":[211],"And":[212],"scheme":[216],"~":[219],"1000\u00d7":[220],"speedup":[221],"compared":[222],"initial":[225],"one.":[226]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}