{"id":"https://openalex.org/W2998273950","doi":"https://doi.org/10.1109/iccad45719.2019.8942087","title":"Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes","display_name":"Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W2998273950","doi":"https://doi.org/10.1109/iccad45719.2019.8942087","mag":"2998273950"},"language":"en","primary_location":{"id":"doi:10.1109/iccad45719.2019.8942087","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad45719.2019.8942087","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://escholarship.org/content/qt4tk647mr/qt4tk647mr.pdf?t=qnzy6r","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002853026","display_name":"Albert Magyar","orcid":"https://orcid.org/0000-0002-4218-3824"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Albert Magyar","raw_affiliation_strings":["University of California, Berkeley"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059660054","display_name":"David Biancolin","orcid":"https://orcid.org/0000-0001-6371-9053"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Biancolin","raw_affiliation_strings":["University of California, Berkeley"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110857178","display_name":"John Koenig","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Koenig","raw_affiliation_strings":["University of California, Berkeley"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064230639","display_name":"Sanjit A. Seshia","orcid":"https://orcid.org/0000-0001-6190-8707"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjit Seshia","raw_affiliation_strings":["University of California, Berkeley"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088484890","display_name":"Jonathan Bachrach","orcid":"https://orcid.org/0000-0002-0533-2712"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Bachrach","raw_affiliation_strings":["University of California, Berkeley"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035134864","display_name":"Krste Asanovi\u0107","orcid":"https://orcid.org/0000-0003-0754-3975"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krste Asanovic","raw_affiliation_strings":["University of California, Berkeley"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5002853026"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":1.9749,"has_fulltext":true,"cited_by_count":14,"citation_normalized_percentile":{"value":0.86761169,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8093235492706299},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.754180908203125},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5864874720573425},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5240837931632996},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.4993429183959961},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4952177107334137},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.4890905022621155},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47124940156936646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45806390047073364},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.42950814962387085},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3634878098964691},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35058683156967163},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.30408528447151184},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16843456029891968},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14902451634407043}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8093235492706299},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.754180908203125},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5864874720573425},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5240837931632996},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.4993429183959961},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4952177107334137},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.4890905022621155},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47124940156936646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45806390047073364},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.42950814962387085},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3634878098964691},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35058683156967163},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.30408528447151184},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16843456029891968},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14902451634407043},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iccad45719.2019.8942087","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad45719.2019.8942087","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},{"id":"pmh:oai:escholarship.org:ark:/13030/qt4tk647mr","is_oa":true,"landing_page_url":"https://escholarship.org/uc/item/4tk647mr","pdf_url":"https://escholarship.org/content/qt4tk647mr/qt4tk647mr.pdf?t=qnzy6r","source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"},{"id":"pmh:oai:escholarship.org:ark:/13030/qt4zs731zk","is_oa":true,"landing_page_url":"https://escholarship.org/uc/item/4zs731zk","pdf_url":"https://escholarship.org/content/qt4zs731zk/qt4zs731zk.pdf?t=qmidtb","source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"}],"best_oa_location":{"id":"pmh:oai:escholarship.org:ark:/13030/qt4tk647mr","is_oa":true,"landing_page_url":"https://escholarship.org/uc/item/4tk647mr","pdf_url":"https://escholarship.org/content/qt4tk647mr/qt4tk647mr.pdf?t=qnzy6r","source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"},"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/8"}],"awards":[{"id":"https://openalex.org/G2782353421","display_name":null,"funder_award_id":"(ARPA-E)","funder_id":"https://openalex.org/F4320332276","funder_display_name":"Advanced Research Projects Agency - Energy"},{"id":"https://openalex.org/G328742790","display_name":null,"funder_award_id":"DE-AR0000849","funder_id":"https://openalex.org/F4320306084","funder_display_name":"U.S. Department of Energy"},{"id":"https://openalex.org/G4848625364","display_name":null,"funder_award_id":"DE-AR000084","funder_id":"https://openalex.org/F4320332276","funder_display_name":"Advanced Research Projects Agency - Energy"},{"id":"https://openalex.org/G909202909","display_name":null,"funder_award_id":"DE-AR0000849","funder_id":"https://openalex.org/F4320332276","funder_display_name":"Advanced Research Projects Agency - Energy"}],"funders":[{"id":"https://openalex.org/F4320306084","display_name":"U.S. Department of Energy","ror":"https://ror.org/01bj3aw27"},{"id":"https://openalex.org/F4320316831","display_name":"Futurewei Technologies","ror":null},{"id":"https://openalex.org/F4320316896","display_name":"Seagate Technology","ror":"https://ror.org/04p1xtv71"},{"id":"https://openalex.org/F4320332276","display_name":"Advanced Research Projects Agency - Energy","ror":"https://ror.org/03q1rgc19"},{"id":"https://openalex.org/F4320332815","display_name":"Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":true,"grobid_xml":false},"content_urls":{"pdf":"https://content.openalex.org/works/W2998273950.pdf"},"referenced_works_count":27,"referenced_works":["https://openalex.org/W80624900","https://openalex.org/W119599369","https://openalex.org/W1524114232","https://openalex.org/W1964471912","https://openalex.org/W2001370577","https://openalex.org/W2023808162","https://openalex.org/W2027069801","https://openalex.org/W2057962492","https://openalex.org/W2066339098","https://openalex.org/W2091158003","https://openalex.org/W2099129242","https://openalex.org/W2109560035","https://openalex.org/W2115294662","https://openalex.org/W2134470641","https://openalex.org/W2137385009","https://openalex.org/W2148658001","https://openalex.org/W2160566592","https://openalex.org/W2482886256","https://openalex.org/W2517156085","https://openalex.org/W2588464298","https://openalex.org/W2771610171","https://openalex.org/W2789489838","https://openalex.org/W2884267664","https://openalex.org/W2904222803","https://openalex.org/W2916452982","https://openalex.org/W4233187670","https://openalex.org/W4240172596"],"related_works":["https://openalex.org/W2357541051","https://openalex.org/W3165307257","https://openalex.org/W2515312339","https://openalex.org/W2145098804","https://openalex.org/W4226211266","https://openalex.org/W2991151827","https://openalex.org/W2130440338","https://openalex.org/W1574518580","https://openalex.org/W2791832526","https://openalex.org/W2161229876"],"abstract_inverted_index":{"We":[0],"present":[1,107],"Golden":[2,35,63,136],"Gate,":[3],"an":[4,13,124],"FPGA-based":[5],"simulation":[6,163],"tool":[7,111],"that":[8,18,72,88,99,112],"decouples":[9],"the":[10,20,38,47,84,89],"timing":[11],"of":[12,19,32,52,70,143],"FPGA":[14,33],"host":[15],"platform":[16],"from":[17],"target":[21],"RTL":[22],"design.":[23],"In":[24],"contrast":[25],"to":[26,45,65,123,138,154,172],"previous":[27],"work":[28],"in":[29],"static":[30],"time-multiplexing":[31],"resources,":[34],"Gate":[36,64,137],"employs":[37],"Latency-Insensitive":[39],"Bounded":[40],"Dataflow":[41],"Network":[42],"(LI-BDN)":[43],"formalism":[44,86],"decompose":[46],"simulator":[48,90,142],"into":[49,162],"subcomponents,":[50],"each":[51],"which":[53],"may":[54],"be":[55],"independently":[56],"and":[57,94],"automatically":[58],"optimized.":[59],"This":[60],"structure":[61],"allows":[62],"support":[66],"a":[67,109,114,140,144,178],"broad":[68],"class":[69],"optimizations":[71,101],"improve":[73],"resource":[74],"utilization":[75,151],"by":[76,152,156,166],"implementing":[77],"FPGA-hostile":[78],"structures":[79],"over":[80],"multiple":[81],"cycles,":[82],"while":[83,128],"LI-BDN":[85],"ensures":[87],"still":[91],"produces":[92],"bit-":[93],"cycle-exact":[95,141],"results.":[96],"To":[97],"verify":[98],"these":[100],"are":[102],"implemented":[103],"correctly,":[104],"we":[105,134,148],"also":[106,129],"LIME,":[108],"model-checking":[110],"provides":[113],"push-button":[115],"flow":[116],"for":[117],"checking":[118],"whether":[119],"optimized":[120],"subcomponents":[121],"adhere":[122],"associated":[125],"correctness":[126],"specification,":[127],"guaranteeing":[130],"forward":[131],"progress.":[132],"Finally,":[133],"use":[135],"generate":[139],"multi-core":[145],"SoC,":[146],"where":[147],"reduce":[149],"LUT":[150],"up":[153],"26%":[155],"coercing":[157],"multi-ported,":[158],"combinationally":[159],"read":[160],"memories":[161],"models":[164],"backed":[165],"time-multiplexed":[167],"block":[168],"RAMs,":[169],"enabling":[170],"us":[171],"simulate":[173],"50%":[174],"more":[175],"cores":[176],"on":[177],"single":[179],"FPGA.":[180]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}