{"id":"https://openalex.org/W2997948262","doi":"https://doi.org/10.1109/iccad45719.2019.8942074","title":"Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction","display_name":"Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W2997948262","doi":"https://doi.org/10.1109/iccad45719.2019.8942074","mag":"2997948262"},"language":"en","primary_location":{"id":"doi:10.1109/iccad45719.2019.8942074","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad45719.2019.8942074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101715115","display_name":"Haocheng Li","orcid":"https://orcid.org/0000-0002-3254-3259"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Haocheng Li","raw_affiliation_strings":["The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052177721","display_name":"Gengjie Chen","orcid":"https://orcid.org/0000-0001-6016-4742"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gengjie Chen","raw_affiliation_strings":["The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003335238","display_name":"Bentian Jiang","orcid":"https://orcid.org/0000-0001-8163-3114"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bentian Jiang","raw_affiliation_strings":["The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101951915","display_name":"Jingsong Chen","orcid":"https://orcid.org/0000-0001-9867-9805"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jingsong Chen","raw_affiliation_strings":["The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Evangeline F. Y. Young","raw_affiliation_strings":["The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5101715115"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":3.3779,"has_fulltext":false,"cited_by_count":52,"citation_normalized_percentile":{"value":0.93014881,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.7877308130264282},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7468266487121582},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6607462167739868},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6221176981925964},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5508633852005005},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.49947142601013184},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.495140939950943},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.49439573287963867},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.49123162031173706},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4611743688583374},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.45855966210365295},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4443104565143585},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4162464141845703},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2111469805240631},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1939840316772461},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.14815762639045715},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12895750999450684},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.10782572627067566}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.7877308130264282},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7468266487121582},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6607462167739868},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6221176981925964},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5508633852005005},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.49947142601013184},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.495140939950943},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.49439573287963867},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.49123162031173706},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4611743688583374},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.45855966210365295},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4443104565143585},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4162464141845703},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2111469805240631},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1939840316772461},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.14815762639045715},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12895750999450684},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.10782572627067566},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad45719.2019.8942074","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad45719.2019.8942074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W771507201","https://openalex.org/W1993999542","https://openalex.org/W2022373121","https://openalex.org/W2027790658","https://openalex.org/W2053902150","https://openalex.org/W2143286762","https://openalex.org/W2163105316","https://openalex.org/W2274826728","https://openalex.org/W2406038381","https://openalex.org/W2605351231","https://openalex.org/W2793662773","https://openalex.org/W2899736003","https://openalex.org/W2900068574","https://openalex.org/W2908860223","https://openalex.org/W2936007546","https://openalex.org/W2938881465","https://openalex.org/W3106036041"],"related_works":["https://openalex.org/W2743305891","https://openalex.org/W4246351405","https://openalex.org/W2048044560","https://openalex.org/W2051886008","https://openalex.org/W2535520145","https://openalex.org/W1716153929","https://openalex.org/W4247760676","https://openalex.org/W1985112711","https://openalex.org/W3199828306","https://openalex.org/W3205162826"],"abstract_inverted_index":{"Detailed":[0],"routing":[1,29],"becomes":[2],"a":[3,45],"crucial":[4],"challenge":[5],"in":[6,36,99],"VLSI":[7],"design":[8,15,19,38,55],"with":[9,65,85,91,109],"shrinking":[10],"feature":[11],"size":[12],"and":[13,53,68],"increasing":[14],"complexity.":[16],"More":[17],"complicated":[18],"rules":[20,56],"were":[21],"added":[22],"to":[23,34],"guarantee":[24],"manufacturability,":[25],"which":[26],"made":[27],"detailed":[28,46],"an":[30],"even":[31],"harder":[32],"task":[33],"achieve":[35],"the":[37,81,92,100,110],"flow.":[39],"In":[40],"this":[41],"paper,":[42],"we":[43],"propose":[44],"router":[47],"that":[48,75],"judiciously":[49],"handles":[50],"hard-to-access":[51],"pins":[52],"new":[54],"including":[57],"length-dependent":[58],"parallel":[59,66],"run":[60],"length":[61],"spacing,":[62],"end-of-line":[63],"spacing":[64],"edges,":[67],"corner-to-corner":[69],"spacing.":[70],"Our":[71],"experimental":[72],"results":[73],"show":[74],"our":[76,89,113],"framework":[77],"can":[78],"effectively":[79],"reduce":[80],"number":[82],"of":[83,95,122],"violations":[84],"comparable":[86],"wirelength.":[87],"Comparing":[88],"algorithm":[90,114],"best":[93],"score":[94,106],"each":[96],"released":[97],"designs":[98],"ISPD'19":[101],"Contest,":[102],"there":[103],"is":[104,126],"2%":[105],"improvement.":[107],"Compared":[108],"state-of-the-art":[111],"work,":[112],"achieves":[115],"69%":[116],"better":[117],"scores.":[118],"The":[119],"source":[120],"code":[121],"Dr.":[123],"CU":[124],"2.0":[125],"available":[127],"at":[128],"https://github.com/cuhk-eda/dr-cu.":[129]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":12},{"year":2021,"cited_by_count":9},{"year":2020,"cited_by_count":7}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}
