{"id":"https://openalex.org/W2771551340","doi":"https://doi.org/10.1109/iccad.2017.8203880","title":"Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)","display_name":"Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)","publication_year":2017,"publication_date":"2017-11-01","ids":{"openalex":"https://openalex.org/W2771551340","doi":"https://doi.org/10.1109/iccad.2017.8203880","mag":"2771551340"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2017.8203880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2017.8203880","pdf_url":null,"source":{"id":"https://openalex.org/S4363608376","display_name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080499552","display_name":"Chak-Wa Pui","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chak-Wa Pui","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052177721","display_name":"Gengjie Chen","orcid":"https://orcid.org/0000-0001-6016-4742"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gengjie Chen","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071995111","display_name":"Yuzhe Ma","orcid":"https://orcid.org/0000-0002-3612-4182"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuzhe Ma","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Evangeline F. Y. Young","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051340429","display_name":"Bei Yu","orcid":"https://orcid.org/0000-0001-6406-4810"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bei Yu","raw_affiliation_strings":["Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, NT","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5080499552"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":5.681,"has_fulltext":false,"cited_by_count":43,"citation_normalized_percentile":{"value":0.97113582,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7970560789108276},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7943768501281738},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6358009576797485},{"id":"https://openalex.org/keywords/contest","display_name":"CONTEST","score":0.5397385954856873},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4324093163013458},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3917885720729828},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3795807361602783},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37795135378837585}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7970560789108276},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7943768501281738},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6358009576797485},{"id":"https://openalex.org/C2777582232","wikidata":"https://www.wikidata.org/wiki/Q5013414","display_name":"CONTEST","level":2,"score":0.5397385954856873},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4324093163013458},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3917885720729828},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3795807361602783},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37795135378837585},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccad.2017.8203880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2017.8203880","pdf_url":null,"source":{"id":"https://openalex.org/S4363608376","display_name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-120412","is_oa":false,"landing_page_url":"http://gateway.isiknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=LinksAMR&SrcApp=PARTNER_APP&DestLinkType=FullRecord&DestApp=WOS&KeyUT=000424863100128","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1963908543","https://openalex.org/W1986026297","https://openalex.org/W2005602803","https://openalex.org/W2014070364","https://openalex.org/W2020549672","https://openalex.org/W2033549713","https://openalex.org/W2075137913","https://openalex.org/W2090971357","https://openalex.org/W2099265105","https://openalex.org/W2138206217","https://openalex.org/W2146232231","https://openalex.org/W2151614223","https://openalex.org/W2154014710","https://openalex.org/W2154302973","https://openalex.org/W2158961316","https://openalex.org/W2166747627","https://openalex.org/W2328615082","https://openalex.org/W2533722497","https://openalex.org/W2535234615","https://openalex.org/W2535860792","https://openalex.org/W2538165366","https://openalex.org/W2554031552","https://openalex.org/W2584883722","https://openalex.org/W2585649541","https://openalex.org/W2595334824","https://openalex.org/W2604486584","https://openalex.org/W2738078952","https://openalex.org/W2751111909","https://openalex.org/W3141147179","https://openalex.org/W4249211602","https://openalex.org/W6674910125","https://openalex.org/W6680484343","https://openalex.org/W6728590132","https://openalex.org/W6743386225"],"related_works":["https://openalex.org/W2946214509","https://openalex.org/W2606108738","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2184011203","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882","https://openalex.org/W2154356865"],"abstract_inverted_index":{"As":[0],"the":[1,19,75,83,88,95,131,145],"complexity":[2],"and":[3,28,46,74,115,136],"scale":[4],"of":[5,11],"circuits":[6],"keep":[7],"growing,":[8],"clocking":[9,32],"architectures":[10],"FPGAs":[12],"have":[13],"become":[14],"more":[15],"complex":[16],"to":[17,25,82,97,102,130,139,144],"meet":[18,30],"timing":[20],"requirement.":[21],"In":[22],"this":[23],"paper,":[24],"optimize":[26],"wirelength":[27,73],"meanwhile":[29],"emerging":[31],"architectural":[33],"constraints,":[34],"we":[35,93],"propose":[36],"several":[37],"detailed":[38],"placement":[39,56,141],"techniques,":[40],"i.e.,":[41],"two-step":[42],"clock":[43],"constraint":[44],"legalization":[45],"chain":[47],"move.":[48],"After":[49],"integrating":[50],"these":[51],"techniques":[52],"into":[53],"our":[54,66,121],"FPGA":[55],"framework,":[57],"experimental":[58],"results":[59,110,142],"on":[60,111],"ISPD":[61,89,113,116],"2017":[62,90,117],"benchmarks":[63,118],"show":[64,119],"that":[65,120],"proposed":[67,122],"approach":[68],"yields":[69],"2.3%":[70],"shorter":[71],"routed":[72],"running":[76],"time":[77],"is":[78,126],"2x":[79],"faster":[80],"compared":[81,143],"first":[84],"place":[85],"winner":[86],"in":[87,106],"contest.":[91],"Moreover,":[92],"explore":[94],"possibilities":[96],"use":[98],"machine":[99],"learning-based":[100],"methods":[101],"predict":[103],"routing":[104],"congestion":[105,123],"UltraScale":[107],"FPGAs.":[108],"Experimental":[109],"both":[112],"2016":[114],"estimation":[124],"model":[125],"a":[127],"good":[128,140],"approximation":[129],"one":[132],"obtained":[133],"from":[134],"Vivado":[135],"can":[137],"lead":[138],"previous":[146],"methods.":[147]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":9},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
