{"id":"https://openalex.org/W4243849801","doi":"https://doi.org/10.1109/iccad.2015.7372603","title":"SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis","display_name":"SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis","publication_year":2015,"publication_date":"2015-11-01","ids":{"openalex":"https://openalex.org/W4243849801","doi":"https://doi.org/10.1109/iccad.2015.7372603"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2015.7372603","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2015.7372603","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006089779","display_name":"Chun-Hong Shih","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"ChunHong Shih","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077205053","display_name":"Yi\u2010Hsiang Lai","orcid":"https://orcid.org/0000-0003-0751-4648"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"YiHsiang Lai","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078604015","display_name":"Jie-Hong R. Jiang","orcid":"https://orcid.org/0000-0002-2279-4732"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"JieHong R. Jiang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":1.6652,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.84077097,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"80","issue":null,"first_page":"442","last_page":"449"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7678670287132263},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6858035922050476},{"id":"https://openalex.org/keywords/pipeline-transport","display_name":"Pipeline transport","score":0.6569772958755493},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5620898604393005},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.4769814610481262},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4406864643096924},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4350017309188843},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.4277571141719818},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.407590389251709},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36170291900634766},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33795636892318726},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.2885892987251282},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13298314809799194},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11660182476043701},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08570939302444458}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7678670287132263},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6858035922050476},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.6569772958755493},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5620898604393005},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.4769814610481262},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4406864643096924},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4350017309188843},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.4277571141719818},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.407590389251709},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36170291900634766},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33795636892318726},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2885892987251282},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13298314809799194},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11660182476043701},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08570939302444458},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2015.7372603","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2015.7372603","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.47999998927116394}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W16511050","https://openalex.org/W1595213177","https://openalex.org/W1974229901","https://openalex.org/W1980924035","https://openalex.org/W1996109622","https://openalex.org/W2050890381","https://openalex.org/W2085176118","https://openalex.org/W2088643059","https://openalex.org/W2099620341","https://openalex.org/W2102327308","https://openalex.org/W2106316647","https://openalex.org/W2108678912","https://openalex.org/W2126251049","https://openalex.org/W2138215210","https://openalex.org/W2160823654","https://openalex.org/W3146839929","https://openalex.org/W4250896517","https://openalex.org/W4253136089","https://openalex.org/W6674946643","https://openalex.org/W6676598928","https://openalex.org/W6683394555"],"related_works":["https://openalex.org/W2116677773","https://openalex.org/W2155261584","https://openalex.org/W2584231425","https://openalex.org/W2150611273","https://openalex.org/W397120980","https://openalex.org/W4207086172","https://openalex.org/W2042919702","https://openalex.org/W4225981436","https://openalex.org/W2156185805","https://openalex.org/W2153246750"],"abstract_inverted_index":{"Performance":[0],"analysis":[1,74],"and":[2,32,62,87,105,124,132,135,160,171,174,196,204,207,223,236,240],"deadlock":[3,92],"verification":[4,93],"are":[5,40,199],"two":[6,144],"critical":[7],"issues":[8],"in":[9,21,68,232],"asynchronous":[10,36],"circuit":[11,139],"design,":[12],"which":[13],"can":[14,228],"be":[15,229],"advantageous":[16],"over":[17],"the":[18,50,142,157,166,176,189,233],"synchronous":[19],"counterpart":[20],"terms":[22],"of":[23,52,57,129,168,178,185,191,238],"robustness":[24],"against":[25,29],"timing":[26],"variability,":[27],"security":[28],"side-channel":[30],"attack,":[31],"other":[33],"benefits.":[34],"Nevertheless,":[35],"design":[37],"automation":[38],"tools":[39],"far":[41],"away":[42],"from":[43,82],"mature.":[44],"In":[45],"this":[46],"paper,":[47],"we":[48,115,146],"advance":[49],"synthesis":[51,150,180,216,237],"quasi-delay":[53],"insensitive":[54],"(QDI)":[55],"circuits":[56],"pre-charged":[58],"half":[59,64],"buffer":[60,65],"(PCHB)":[61],"weak-conditioned":[63],"(WCHB)":[66],"pipelines":[67,107,126,206],"three":[69],"respects.":[70],"First,":[71],"static":[72],"performance":[73],"(SPA)":[75],"with":[76,96,182],"linear":[77,97],"time":[78,98],"complexity":[79,99],"is":[80,100,136,212],"generalized":[81],"acyclic":[83],"to":[84,138,201,214],"cyclic":[85],"PCHB":[86,104,123,203,239],"WCHB":[88,106,125,205,241],"pipelines.":[89,242],"Second,":[90],"a":[91,117],"(DV)":[94],"algorithm":[95,211],"proposed":[101],"for":[102,122,152],"checking":[103],"using":[108],"their":[109],"four-phase":[110],"marked":[111],"graph":[112],"models.":[113],"Third,":[114],"propose":[116],"new":[118],"simple":[119],"register":[120],"circuitry":[121],"that":[127],"consists":[128],"one":[130,133],"reset-latch":[131],"buffer-latch":[134,153,209],"amenable":[137],"minimization.":[140],"With":[141],"above":[143],"algorithms,":[145],"develop":[147],"an":[148,183],"efficient":[149],"flow":[151],"minimization":[154,210],"while":[155],"maintaining":[156],"system":[158],"throughput":[159],"deadlock-free":[161],"property.":[162],"Experimental":[163],"results":[164],"show":[165],"efficiency":[167],"our":[169,179,194,208,226],"SPA":[170,195],"DV":[172,197],"algorithms":[173,198],"demonstrate":[175],"effectiveness":[177],"method":[181],"average":[184],"37%":[186],"reduction":[187],"on":[188],"number":[190],"buffer-laches.":[192],"As":[193],"applicable":[200],"arbitrary":[202],"orthogonal":[213],"existing":[215],"methods":[217,227],"such":[218],"as":[219],"cut-based":[220],"technology":[221],"mapping":[222],"slack":[224],"matching,":[225],"generally":[230],"useful":[231],"analysis,":[234],"verification,":[235]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}