{"id":"https://openalex.org/W4253089744","doi":"https://doi.org/10.1109/iccad.2013.6691192","title":"Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop insertion","display_name":"Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop insertion","publication_year":2013,"publication_date":"2013-11-01","ids":{"openalex":"https://openalex.org/W4253089744","doi":"https://doi.org/10.1109/iccad.2013.6691192"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2013.6691192","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2013.6691192","pdf_url":null,"source":{"id":"https://openalex.org/S4363608415","display_name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073558386","display_name":"Andrew B. Kahng","orcid":"https://orcid.org/0000-0002-4490-5018"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Andrew B. Kahng","raw_affiliation_strings":["CSE Department, CA"],"affiliations":[{"raw_affiliation_string":"CSE Department, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008689590","display_name":"Ilgweon Kang","orcid":"https://orcid.org/0000-0003-3842-5613"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ilgweon Kang","raw_affiliation_strings":["CSE Department, CA"],"affiliations":[{"raw_affiliation_string":"CSE Department, CA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101615907","display_name":"Siddhartha Nath","orcid":"https://orcid.org/0000-0002-4848-3385"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Siddhartha Nath","raw_affiliation_strings":["CSE Department, CA"],"affiliations":[{"raw_affiliation_string":"CSE Department, CA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5073558386"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1945,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.44915254,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"44","issue":null,"first_page":"705","last_page":"712"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.8867348432540894},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6582645773887634},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.655727744102478},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.6114197969436646},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5651417374610901},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5557135343551636},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5180097222328186},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.46973809599876404},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.44300922751426697},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4026232957839966},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.38787758350372314},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3518480658531189},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3497769236564636},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.31026339530944824},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20004180073738098},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.13090768456459045},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.11278825998306274},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09991812705993652}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.8867348432540894},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6582645773887634},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.655727744102478},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.6114197969436646},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5651417374610901},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5557135343551636},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5180097222328186},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.46973809599876404},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.44300922751426697},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4026232957839966},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.38787758350372314},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3518480658531189},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3497769236564636},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.31026339530944824},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20004180073738098},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.13090768456459045},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.11278825998306274},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09991812705993652},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2013.6691192","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2013.6691192","pdf_url":null,"source":{"id":"https://openalex.org/S4363608415","display_name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1546457065","https://openalex.org/W1970462306","https://openalex.org/W1972740534","https://openalex.org/W1975828823","https://openalex.org/W2011039300","https://openalex.org/W2018660239","https://openalex.org/W2029681015","https://openalex.org/W2039130539","https://openalex.org/W2050819731","https://openalex.org/W2068123526","https://openalex.org/W2103423925","https://openalex.org/W2111563176","https://openalex.org/W2115821030","https://openalex.org/W2118966417","https://openalex.org/W2154653362","https://openalex.org/W2154800965","https://openalex.org/W2167083462","https://openalex.org/W2171905707","https://openalex.org/W2324108981","https://openalex.org/W3127555477","https://openalex.org/W4236269389","https://openalex.org/W4245500163","https://openalex.org/W4302458519","https://openalex.org/W6654935975","https://openalex.org/W6789937620"],"related_works":["https://openalex.org/W2947266479","https://openalex.org/W2369589212","https://openalex.org/W2118952760","https://openalex.org/W2107525390","https://openalex.org/W2075356617","https://openalex.org/W2157191248","https://openalex.org/W1974621628","https://openalex.org/W3088373974","https://openalex.org/W2141620082","https://openalex.org/W2789575913"],"abstract_inverted_index":{"Testability":[0],"of":[1,34,78],"ECO":[2,37],"logic":[3],"is":[4],"currently":[5],"a":[6,63,87],"significant":[7],"bottleneck":[8],"in":[9],"the":[10,73,98],"SOC":[11],"implementation":[12],"flow.":[13],"Front-end":[14],"designers":[15],"sometimes":[16],"require":[17],"large":[18,82],"functional":[19,83],"ECOs":[20],"close":[21],"to":[22,49,71,96,108,133],"scheduled":[23],"tapeout":[24],"dates":[25],"or":[26],"for":[27,81,114],"later":[28],"design":[29],"revisions.":[30],"To":[31],"avoid":[32],"loss":[33],"test":[35,50],"coverage,":[36],"flip-flops":[38],"must":[39],"be":[40],"added":[41],"into":[42],"existing":[43,56,109],"scan":[44,79,110,117],"chains":[45],"with":[46,89],"minimal":[47,53],"increase":[48],"time":[51],"and":[52,58,75,93,106,124],"impact":[54],"on":[55],"routing":[57,104],"timing":[59],"slack.":[60],"We":[61,85],"address":[62],"new":[64],"Incremental":[65],"Multiple-Scan":[66],"Chain":[67],"Ordering":[68],"problem":[69],"formulation":[70],"automate":[72],"tedious":[74],"time-consuming":[76],"process":[77],"stitching":[80],"ECOs.":[84],"present":[86],"heuristic":[88],"clustering,":[90],"incremental":[91,116,125],"clustering":[92],"ordering":[94],"steps":[95],"minimize":[97],"maximum":[99],"chain":[100,118],"length":[101],"(test":[102],"time),":[103],"congestion,":[105],"disturbance":[107],"chains.":[111],"Test":[112],"times":[113],"our":[115],"solutions":[119],"are":[120,128],"reduced":[121,129],"by":[122,130],"5.3%,":[123],"wirelength":[126],"costs":[127],"45.71%,":[131],"compared":[132],"manually-solved":[134],"industrial":[135],"testcases.":[136]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}