{"id":"https://openalex.org/W3146960355","doi":"https://doi.org/10.1109/iccad.2011.6105401","title":"MACACO: Modeling and analysis of circuits for approximate computing","display_name":"MACACO: Modeling and analysis of circuits for approximate computing","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W3146960355","doi":"https://doi.org/10.1109/iccad.2011.6105401","mag":"3146960355"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2011.6105401","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045219356","display_name":"Rangharajan Venkatesan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rangharajan Venkatesan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074819032","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-3933-5014"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0002-0735-9695"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065766721","display_name":"Anand Raghunathan","orcid":"https://orcid.org/0000-0002-4624-564X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Anand Raghunathan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":204,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"667","last_page":"673"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7007242441177368},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.6094755530357361},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5014710426330566},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4981224536895752},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.49635130167007446},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.4472537636756897},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.44638770818710327},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.44182634353637695},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4378425180912018},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.4363937973976135},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.4355488717556},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.4350561201572418},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.37618327140808105},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3626561462879181},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.21907278895378113},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21714550256729126},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19099384546279907}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7007242441177368},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.6094755530357361},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5014710426330566},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4981224536895752},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.49635130167007446},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.4472537636756897},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.44638770818710327},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.44182634353637695},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4378425180912018},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.4363937973976135},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.4355488717556},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.4350561201572418},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37618327140808105},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3626561462879181},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.21907278895378113},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21714550256729126},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19099384546279907},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2011.6105401","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W139069461","https://openalex.org/W1569305728","https://openalex.org/W2003957094","https://openalex.org/W2010468809","https://openalex.org/W2088706828","https://openalex.org/W2105562886","https://openalex.org/W2106484393","https://openalex.org/W2119422129","https://openalex.org/W2121205475","https://openalex.org/W2124616298","https://openalex.org/W2126044301","https://openalex.org/W2128065014","https://openalex.org/W2150813825","https://openalex.org/W2155458498","https://openalex.org/W2156425544","https://openalex.org/W2296253867","https://openalex.org/W3141620748","https://openalex.org/W3143757450","https://openalex.org/W3149545534","https://openalex.org/W3149572347","https://openalex.org/W4236432903","https://openalex.org/W4245015178","https://openalex.org/W4253998042","https://openalex.org/W4255029913","https://openalex.org/W6605757176","https://openalex.org/W6634116098","https://openalex.org/W6676258682","https://openalex.org/W6678801464"],"related_works":["https://openalex.org/W2111251553","https://openalex.org/W21388859","https://openalex.org/W3148693912","https://openalex.org/W2120549874","https://openalex.org/W2156069452","https://openalex.org/W4210841712","https://openalex.org/W2045146060","https://openalex.org/W3046927439","https://openalex.org/W2114722319","https://openalex.org/W4242390528"],"abstract_inverted_index":{"Approximate":[0,47],"computing,":[1],"which":[2],"refers":[3],"to":[4,55,64,86,172,185,205,214],"a":[5,22,34,65,126,135,187,203],"class":[6],"of":[7,13,21,44,112,121,177,189,210,224],"techniques":[8,161,167],"that":[9,117,139,199],"relax":[10],"the":[11,17,40,110,119,122,141,144,174,182,208,222],"requirement":[12],"exact":[14],"equivalence":[15],"between":[16,216],"specification":[18],"and":[19,42,80,96,129,165,213],"implementation":[20],"computing":[23,70],"system,":[24],"has":[25],"attracted":[26],"significant":[27],"interest":[28],"in":[29,107,143,170],"recent":[30],"years.":[31],"We":[32,179],"propose":[33],"systematic":[35],"methodology,":[36],"called":[37],"MACACO,":[38],"for":[39,46,148,192,227],"Modeling":[41],"Analysis":[43],"Circuits":[45],"Computing.":[48],"The":[49,83,104],"proposed":[50,183],"methodology":[51,84,184],"can":[52,201],"be":[53],"utilized":[54],"analyze":[56,186],"how":[57],"an":[58,113],"approximate":[59,123,145,190,211,218,228],"circuit":[60,116,124,138],"behaves":[61],"with":[62],"reference":[63],"conventional":[66,158],"correct":[67],"implementation,":[68],"by":[69],"metrics":[71,176],"such":[72,90,225],"as":[73,91],"worst-case":[74],"error,":[75,77],"average-case":[76],"error":[78,81,137,142],"probability,":[79],"distribution.":[82],"applies":[85],"both":[87],"timing-induced":[88],"approximations":[89,98],"voltage":[92,128],"over-scaling":[93],"or":[94,152],"over-clocking,":[95],"functional":[97],"based":[99],"on":[100],"logic":[101],"complexity":[102],"reduction.":[103],"first":[105],"step":[106],"MACACO":[108,200],"is":[109],"construction":[111],"equivalent":[114],"untimed":[115],"represents":[118,140],"behavior":[120],"at":[125],"given":[127,150],"clock":[130],"period.":[131],"Next,":[132],"we":[133,156],"construct":[134],"virtual":[136],"circuit's":[146],"output":[147],"any":[149],"input":[151,153],"sequence.":[154],"Finally,":[155],"apply":[157],"Boolean":[159],"analysis":[160],"(SAT":[162],"solvers,":[163],"BDDs)":[164],"statistical":[166],"(Monte-Carlo":[168],"simulation)":[169],"order":[171],"compute":[173],"various":[175],"interest.":[178],"have":[180],"applied":[181],"range":[188],"designs":[191],"datapath":[193],"building":[194],"blocks.":[195],"Our":[196],"results":[197],"show":[198],"help":[202],"designer":[204],"systematically":[206],"evaluate":[207],"impact":[209],"circuits,":[212],"choose":[215],"different":[217],"implementations,":[219],"thereby":[220],"facilitating":[221],"adoption":[223],"circuits":[226],"computing.":[229]},"counts_by_year":[{"year":2026,"cited_by_count":6},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":14},{"year":2022,"cited_by_count":13},{"year":2021,"cited_by_count":15},{"year":2020,"cited_by_count":23},{"year":2019,"cited_by_count":15},{"year":2018,"cited_by_count":26},{"year":2017,"cited_by_count":17},{"year":2016,"cited_by_count":13},{"year":2015,"cited_by_count":15},{"year":2014,"cited_by_count":18},{"year":2013,"cited_by_count":10},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}