{"id":"https://openalex.org/W3136963889","doi":"https://doi.org/10.1109/iccad.2011.6105378","title":"Heterogeneous B&lt;sup&gt;&amp;#x2217;&lt;/sup&gt;-trees for analog placement with symmetry and regularity considerations","display_name":"Heterogeneous B&lt;sup&gt;&amp;#x2217;&lt;/sup&gt;-trees for analog placement with symmetry and regularity considerations","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W3136963889","doi":"https://doi.org/10.1109/iccad.2011.6105378","mag":"3136963889"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2011.6105378","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105378","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034615401","display_name":"Pang-Yen Chou","orcid":"https://orcid.org/0000-0003-2435-9811"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Pang-Yen Chou","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076824306","display_name":"Hung-Chih Ou","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Chih Ou","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5034615401"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.265,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67161887,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"512","last_page":"516"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/symmetry","display_name":"Symmetry (geometry)","score":0.7142768502235413},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6950716972351074},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.6717166304588318},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6685442924499512},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.6418313384056091},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5347190499305725},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5299972891807556},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4848690927028656},{"id":"https://openalex.org/keywords/work","display_name":"Work (physics)","score":0.47310519218444824},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4652465581893921},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4004761874675751},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3950746953487396},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3781498074531555},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.32131296396255493},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.23954805731773376},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.21819299459457397},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.2068152129650116},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.18686780333518982},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14123374223709106},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1404181718826294}],"concepts":[{"id":"https://openalex.org/C2779886137","wikidata":"https://www.wikidata.org/wiki/Q21030012","display_name":"Symmetry (geometry)","level":2,"score":0.7142768502235413},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6950716972351074},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.6717166304588318},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6685442924499512},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.6418313384056091},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5347190499305725},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5299972891807556},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4848690927028656},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.47310519218444824},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4652465581893921},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4004761874675751},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3950746953487396},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3781498074531555},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.32131296396255493},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.23954805731773376},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.21819299459457397},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.2068152129650116},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.18686780333518982},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14123374223709106},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1404181718826294},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2011.6105378","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105378","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2003837070","https://openalex.org/W2043503568","https://openalex.org/W2100740271","https://openalex.org/W2105010240","https://openalex.org/W2106241469","https://openalex.org/W2117754533","https://openalex.org/W2146519106","https://openalex.org/W3144327609","https://openalex.org/W3145854928","https://openalex.org/W4242618871","https://openalex.org/W4242842879","https://openalex.org/W4247078132","https://openalex.org/W4249900664","https://openalex.org/W6675602057"],"related_works":["https://openalex.org/W85694287","https://openalex.org/W2076658455","https://openalex.org/W2158511068","https://openalex.org/W2885948601","https://openalex.org/W4241171805","https://openalex.org/W2020253769","https://openalex.org/W2143930978","https://openalex.org/W4239381562","https://openalex.org/W2167484077","https://openalex.org/W2108092114"],"abstract_inverted_index":{"Symmetry":[0,14],"constraints":[1,15],"and":[2,45,54,69,74,114,126,133],"regular":[3],"structures":[4,35],"are":[5,16,36,83],"two":[6],"major":[7],"considerations":[8],"for":[9,80],"expert":[10],"analog":[11],"layout":[12],"designers.":[13],"specified":[17],"to":[18,25,29,42,66],"place":[19],"matched":[20],"modules":[21],"symmetrically":[22],"with":[23],"respect":[24],"some":[26],"common":[27],"axes":[28],"reduce":[30],"unwanted":[31],"electrical":[32],"effects.":[33],"Regular":[34],"commonly":[37],"followed":[38],"by":[39,49],"experienced":[40],"designers":[41],"enhance":[43],"routability":[44],"suppress":[46],"parasitics":[47],"induced":[48],"extra":[50],"bends":[51],"of":[52],"wires":[53],"via":[55],"cost.":[56],"In":[57],"this":[58],"paper,":[59],"we":[60],"propose":[61],"a":[62,75,107],"heterogeneous":[63],"B*-tree":[64],"representation":[65,82],"consider":[67],"symmetry":[68,100],"regularity":[70,77],"simultaneously.":[71],"Corresponding":[72],"moves":[73],"new":[76],"cost":[78],"modelling":[79],"the":[81,119],"also":[84],"presented.":[85],"Experimental":[86],"results":[87],"show":[88],"that":[89],"our":[90,104],"approach":[91],"can":[92],"efficiently":[93],"generate":[94],"regularly":[95],"structured":[96],"placement":[97,124],"satisfying":[98],"all":[99],"constraints.":[101],"For":[102],"example,":[103],"placer":[105],"achieves":[106],"18X":[108],"runtime":[109],"speedup,":[110],"28%":[111],"smaller":[112],"area,":[113],"68%":[115],"shorter":[116,135],"wirelength":[117],"than":[118],"previous":[120],"work,":[121],"based":[122,138],"on":[123,139],"results,":[125],"60%":[127],"fewer":[128,131],"overflows,":[129],"39%":[130],"vias,":[132],"86%":[134],"routed":[136],"wirelength,":[137],"global":[140],"routing":[141],"results.":[142]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
