{"id":"https://openalex.org/W3151056235","doi":"https://doi.org/10.1109/iccad.2011.6105376","title":"A methodology for local resonant clock synthesis using LC-assisted local clock buffers","display_name":"A methodology for local resonant clock synthesis using LC-assisted local clock buffers","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W3151056235","doi":"https://doi.org/10.1109/iccad.2011.6105376","mag":"3151056235"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2011.6105376","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105376","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088329648","display_name":"Walter J. Condley","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Walter J. Condley","raw_affiliation_strings":["Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043295750","display_name":"Xuchu Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xuchu Hu","raw_affiliation_strings":["Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065218759","display_name":"Matthew R. Guthaus","orcid":"https://orcid.org/0000-0002-8113-4531"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew R. Guthaus","raw_affiliation_strings":["Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5088329648"],"corresponding_institution_ids":["https://openalex.org/I185103710"],"apc_list":null,"apc_paid":null,"fwci":0.5299,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.73654376,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"503","last_page":"506"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.796330988407135},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.6767913699150085},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6647413969039917},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.561803936958313},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.544609785079956},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5246726870536804},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.49814486503601074},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4965978264808655},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4921940863132477},{"id":"https://openalex.org/keywords/adiabatic-process","display_name":"Adiabatic process","score":0.4918961524963379},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4894210398197174},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4722708463668823},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4251488149166107},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3692418038845062},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2614666223526001},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2611459791660309},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22950416803359985}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.796330988407135},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6767913699150085},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6647413969039917},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.561803936958313},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.544609785079956},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5246726870536804},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.49814486503601074},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4965978264808655},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4921940863132477},{"id":"https://openalex.org/C109663097","wikidata":"https://www.wikidata.org/wiki/Q182453","display_name":"Adiabatic process","level":2,"score":0.4918961524963379},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4894210398197174},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4722708463668823},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4251488149166107},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3692418038845062},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2614666223526001},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2611459791660309},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22950416803359985},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2011.6105376","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105376","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1507707340","https://openalex.org/W2025516544","https://openalex.org/W2066332052","https://openalex.org/W2122724421","https://openalex.org/W2127083609","https://openalex.org/W2128060653","https://openalex.org/W2145222465","https://openalex.org/W2148201816","https://openalex.org/W2158130267","https://openalex.org/W2166694777","https://openalex.org/W4246466063","https://openalex.org/W6682419823"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W2088914741","https://openalex.org/W2559451387","https://openalex.org/W4247180033","https://openalex.org/W2137310043","https://openalex.org/W2337711143","https://openalex.org/W3006003651","https://openalex.org/W2090213929","https://openalex.org/W3199387640","https://openalex.org/W2617666058"],"abstract_inverted_index":{"Resonant":[0],"clocking":[1,7,70],"is":[2],"a":[3,48],"form":[4,67],"of":[5,11,68],"adiabatic":[6,69],"that":[8,65],"retains":[9],"much":[10,76],"the":[12,22,31],"energy":[13],"present":[14,30],"in":[15,59],"clock":[16,24,38,82],"switching":[17],"and":[18],"recycles":[19],"it":[20],"into":[21],"following":[23],"cycle.":[25],"In":[26],"this":[27,66],"paper":[28],"we":[29],"first":[32],"automated":[33],"methodology":[34],"using":[35],"LC-assisted":[36],"local":[37,43],"buffers":[39],"(LCLCB)":[40],"for":[41],"generating":[42],"resonant":[44],"clocks.":[45],"This":[46],"uses":[47],"single-buffer":[49],"single-inductor":[50],"sector":[51],"topology":[52],"applied":[53],"to":[54],"non-uniform":[55],"trees":[56],"as":[57,75,77],"found":[58],"most":[60],"ASIC":[61],"designs.":[62],"We":[63],"show":[64],"can":[71],"achieve":[72],"power":[73],"savings":[74],"75%":[78],"over":[79],"traditional":[80],"buffered":[81],"networks.":[83]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
