{"id":"https://openalex.org/W3145367831","doi":"https://doi.org/10.1109/iccad.2011.6105357","title":"Delay optimization using SOP balancing","display_name":"Delay optimization using SOP balancing","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W3145367831","doi":"https://doi.org/10.1109/iccad.2011.6105357","mag":"3145367831"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2011.6105357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105357","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["Department of EECS, University of California Berkeley, USA"],"affiliations":[{"raw_affiliation_string":"Department of EECS, University of California Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064568178","display_name":"Robert K. Brayton","orcid":"https://orcid.org/0000-0002-3861-1718"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Brayton","raw_affiliation_strings":["Department of EECS, University of California Berkeley, USA"],"affiliations":[{"raw_affiliation_string":"Department of EECS, University of California Berkeley, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017420100","display_name":"Stephen Jang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Stephen Jang","raw_affiliation_strings":["Agate Logic Inc., USA"],"affiliations":[{"raw_affiliation_string":"Agate Logic Inc., USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038911613","display_name":"\u0412. \u0412. \u041a\u0440\u0430\u0432\u0435\u0446","orcid":"https://orcid.org/0000-0002-4475-5427"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Victor Kravets","raw_affiliation_strings":["IBM, Corporation, USA"],"affiliations":[{"raw_affiliation_string":"IBM, Corporation, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5110450560"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":0.5179,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.71278865,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"375","last_page":"382"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7817384004592896},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7311388254165649},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6831986308097839},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6048115491867065},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5798653960227966},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5759634971618652},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5279468894004822},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.44815337657928467},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4410621225833893},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4341456890106201},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4335186183452606},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.43049126863479614},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42816638946533203},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.359819233417511},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3426748514175415},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.2088768184185028},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.18072134256362915},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.15012896060943604},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10727187991142273},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09300857782363892}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7817384004592896},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7311388254165649},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6831986308097839},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6048115491867065},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5798653960227966},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5759634971618652},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5279468894004822},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.44815337657928467},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4410621225833893},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4341456890106201},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4335186183452606},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.43049126863479614},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42816638946533203},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.359819233417511},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3426748514175415},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.2088768184185028},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.18072134256362915},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.15012896060943604},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10727187991142273},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09300857782363892},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2011.6105357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105357","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W35668030","https://openalex.org/W1511688816","https://openalex.org/W1528837436","https://openalex.org/W1548459443","https://openalex.org/W2010477071","https://openalex.org/W2025617772","https://openalex.org/W2042714660","https://openalex.org/W2043179331","https://openalex.org/W2100955320","https://openalex.org/W2105715355","https://openalex.org/W2106282646","https://openalex.org/W2114556285","https://openalex.org/W2119708813","https://openalex.org/W2124786832","https://openalex.org/W2125803098","https://openalex.org/W2140132043","https://openalex.org/W2145806390","https://openalex.org/W2147774239","https://openalex.org/W3143290261","https://openalex.org/W3144903090","https://openalex.org/W4240866746","https://openalex.org/W4251954744","https://openalex.org/W4256548512","https://openalex.org/W6601412428","https://openalex.org/W6631725144","https://openalex.org/W6675636599","https://openalex.org/W6676950945","https://openalex.org/W6678753650"],"related_works":["https://openalex.org/W2031753133","https://openalex.org/W2269990635","https://openalex.org/W2080129643","https://openalex.org/W2543290882","https://openalex.org/W2295153704","https://openalex.org/W2051041430","https://openalex.org/W2151657833","https://openalex.org/W1554205582","https://openalex.org/W3111996845","https://openalex.org/W1979439610"],"abstract_inverted_index":{"Reducing":[0],"delay":[1,33,67,123],"of":[2,92,109,148,154],"a":[3,22,47,93,100,110,155],"digital":[4],"circuit":[5],"is":[6,44,53],"an":[7],"important":[8],"topic":[9],"in":[10,46,77,86,120,140],"logic":[11,142],"synthesis":[12,28,95],"for":[13],"standard":[14,69,113],"cells":[15],"and":[16,25,43,96,122],"LUT-based":[17],"FPGAs.":[18],"This":[19],"paper":[20],"presents":[21],"simple,":[23],"fast,":[24],"very":[26],"efficient":[27],"algorithm":[29,38,104,131],"to":[30,40,118],"improve":[31,66],"the":[32,63,75,84,103,130,146],"after":[34,68,124],"technology":[35,49],"mapping.":[36,157],"The":[37,51],"scales":[39],"large":[41],"designs":[42,60],"implemented":[45],"publicly-available":[48],"mapper.":[50],"code":[52],"available":[54],"online.":[55],"Experimental":[56],"results":[57],"on":[58,90,152],"industrial":[59,112],"show":[61],"that":[62],"method":[64],"can":[65],"cell":[70,114],"mapping":[71,97,136],"by":[72,81,88],"30%":[73],"with":[74,83],"increase":[76,85,151],"area":[78,87,121,150],"2.4%,":[79],"or":[80],"41%":[82],"3.9%,":[89],"top":[91,153],"high-effort":[94,156],"flow.":[98],"In":[99,126],"separate":[101],"experiment,":[102,129],"was":[105,132],"used":[106],"as":[107],"part":[108],"complete":[111],"design":[115],"flow,":[116],"leading":[117],"improvements":[119],"place-and-route.":[125],"yet":[127],"another":[128],"applied":[133],"before":[134],"FPGA":[135],"into":[137],"4-LUTs,":[138],"resulting":[139],"16%":[141],"level":[143],"reduction":[144],"at":[145],"cost":[147],"9%":[149]},"counts_by_year":[{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}
