{"id":"https://openalex.org/W3142815259","doi":"https://doi.org/10.1109/iccad.2011.6105304","title":"Bandwidth-aware reconfigurable cache design with hybrid memory technologies","display_name":"Bandwidth-aware reconfigurable cache design with hybrid memory technologies","publication_year":2011,"publication_date":"2011-11-01","ids":{"openalex":"https://openalex.org/W3142815259","doi":"https://doi.org/10.1109/iccad.2011.6105304","mag":"3142815259"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2011.6105304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105304","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077387335","display_name":"Jishen Zhao","orcid":"https://orcid.org/0000-0002-1969-743X"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jishen Zhao","raw_affiliation_strings":["Computer Science and Engineering Department, Pennsylvania State University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering Department, Pennsylvania State University, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101777595","display_name":"Cong Xu","orcid":"https://orcid.org/0000-0002-9278-1363"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cong Xu","raw_affiliation_strings":["Computer Science and Engineering Department, Pennsylvania State University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering Department, Pennsylvania State University, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056412895","display_name":"Yuan Xie","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuan Xie","raw_affiliation_strings":["Computer Science and Engineering Department, Pennsylvania State University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering Department, Pennsylvania State University, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130769515"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.25768881,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"48","last_page":"55"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8367253541946411},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6266211867332458},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5143419504165649},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.493071049451828},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.46610507369041443},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4602772891521454},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.445894718170166},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.43558216094970703},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4287126362323761},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.42816662788391113},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.42540615797042847},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.4218830168247223},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3958437442779541},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.39292722940444946},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3863184154033661},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.35485389828681946},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.28971952199935913},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.2865697741508484},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.27777671813964844},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18700695037841797},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18529799580574036}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8367253541946411},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6266211867332458},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5143419504165649},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.493071049451828},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.46610507369041443},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4602772891521454},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.445894718170166},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.43558216094970703},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4287126362323761},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.42816662788391113},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.42540615797042847},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.4218830168247223},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3958437442779541},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.39292722940444946},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3863184154033661},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.35485389828681946},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.28971952199935913},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.2865697741508484},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.27777671813964844},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18700695037841797},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18529799580574036}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccad.2011.6105304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2011.6105304","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-133624","is_oa":false,"landing_page_url":"http://www.scopus.com/record/display.url?eid=2-s2.0-84862971010&origin=inward","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.75}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W178585798","https://openalex.org/W1985868795","https://openalex.org/W1991301369","https://openalex.org/W1992180455","https://openalex.org/W2021388492","https://openalex.org/W2025441862","https://openalex.org/W2064977311","https://openalex.org/W2072753794","https://openalex.org/W2084007230","https://openalex.org/W2092608522","https://openalex.org/W2097927681","https://openalex.org/W2100913437","https://openalex.org/W2102255233","https://openalex.org/W2109631284","https://openalex.org/W2120635877","https://openalex.org/W2145871983","https://openalex.org/W2155503253","https://openalex.org/W2169875292","https://openalex.org/W4244814458","https://openalex.org/W4248310916","https://openalex.org/W4255545170","https://openalex.org/W4255616683","https://openalex.org/W6675347859","https://openalex.org/W6680960445","https://openalex.org/W6681352259"],"related_works":["https://openalex.org/W2807409404","https://openalex.org/W2606565524","https://openalex.org/W2350803493","https://openalex.org/W2570594754","https://openalex.org/W2735130281","https://openalex.org/W1531802798","https://openalex.org/W2586378910","https://openalex.org/W15724499","https://openalex.org/W2021535927","https://openalex.org/W79990711"],"abstract_inverted_index":{"In":[0,37],"chip-multiprocessor":[1],"(CMP)":[2],"designs,":[3,144],"limited":[4],"memory":[5,16,21,24,33,50,73],"bandwidth":[6,82,109],"is":[7,88,115],"a":[8,42,55,59,63,93,132],"potential":[9],"bottleneck":[10],"of":[11,54,102,111,134],"the":[12,81,85,99,107,123,149],"system":[13,124,150],"performance.":[14],"New":[15],"technologies,":[17],"such":[18],"as":[19],"spin-torque-transfer":[20],"(STT-RAM),":[22],"resistive":[23],"(RRAM),":[25],"and":[26,62,136,154,158],"embedded":[27],"DRAM":[28],"(eDRAM),":[29],"are":[30],"promising":[31],"on-chip":[32],"solutions":[34],"for":[35,156],"CMPs.":[36],"this":[38],"paper,":[39],"we":[40,91],"propose":[41],"bandwidth-aware":[43],"re-configurable":[44],"cache":[45,57,69,100,143],"hierarchy":[46,70,87],"(BARCH)":[47],"with":[48,131],"hybrid":[49,56,68],"technologies.":[51],"BARCH":[52],"consists":[53],"hierarchy,":[58],"reconfiguration":[60,94],"mechanism,":[61],"statistical":[64],"prediction":[65,119],"engine.":[66,120],"Our":[67],"chooses":[71],"different":[72,112],"technologies":[74],"to":[75,96,140],"configure":[76],"each":[77,103],"level":[78,104],"so":[79],"that":[80],"provided":[83],"by":[84,117,128,152],"overall":[86],"optimized.":[89],"Furthermore,":[90],"present":[92],"mechanism":[95],"dynamically":[97],"adapt":[98],"space":[101],"based":[105],"on":[106],"predicted":[108],"demands":[110],"applications,":[113,160],"which":[114],"guaranteed":[116],"our":[118,129,145],"We":[121],"evaluate":[122],"performance":[125],"gain":[126],"obtained":[127],"method":[130],"set":[133],"multithreaded":[135,157],"multiprogrammed":[137,159],"applications.":[138],"Compared":[139],"traditional":[141],"SRAM-based":[142],"proposed":[146],"design":[147],"improves":[148],"throughput":[151],"58%":[153],"14%":[155],"respectively.":[161]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}