{"id":"https://openalex.org/W4247344326","doi":"https://doi.org/10.1109/iccad.2010.5654234","title":"Design-hierarchy aware mixed-size placement for routability optimization","display_name":"Design-hierarchy aware mixed-size placement for routability optimization","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W4247344326","doi":"https://doi.org/10.1109/iccad.2010.5654234"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2010.5654234","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2010.5654234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075696706","display_name":"Yi-Lin Chuang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yi-Lin Chuang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043138186","display_name":"Gi-Joon Nam","orcid":"https://orcid.org/0000-0001-6355-2935"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gi-Joon Nam","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113656006","display_name":"Charles J. Alpert","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles J. Alpert","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110108098","display_name":"Jarrod A. Roy","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jarrod Roy","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"last","author":{"id":null,"display_name":"Natarajan Viswanathan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Natarajan Viswanathan","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5075696706"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.8826,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.79626269,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"663","last_page":"668"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7579517364501953},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.6833876967430115},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6045398116111755},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.5729612708091736},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5553551912307739},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5374712347984314},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5107324123382568},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.4798673987388611},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.44160011410713196},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.43062055110931396},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.42731598019599915},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.39719080924987793},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3528977334499359},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2360031008720398},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2204066812992096},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.20718401670455933},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2050902545452118},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13165217638015747}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7579517364501953},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.6833876967430115},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6045398116111755},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.5729612708091736},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5553551912307739},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5374712347984314},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5107324123382568},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.4798673987388611},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.44160011410713196},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.43062055110931396},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.42731598019599915},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.39719080924987793},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3528977334499359},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2360031008720398},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2204066812992096},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.20718401670455933},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2050902545452118},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13165217638015747},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2010.5654234","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2010.5654234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","score":0.5400000214576721,"id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1972047514","https://openalex.org/W2002525234","https://openalex.org/W2011912079","https://openalex.org/W2090317622","https://openalex.org/W2114871550","https://openalex.org/W2132823746","https://openalex.org/W2132915653","https://openalex.org/W2133367791","https://openalex.org/W2144642377","https://openalex.org/W2149098716","https://openalex.org/W2155462145","https://openalex.org/W2160181657","https://openalex.org/W2167190617","https://openalex.org/W2997394943","https://openalex.org/W3145225676","https://openalex.org/W6679151251","https://openalex.org/W6681593708"],"related_works":["https://openalex.org/W1969091636","https://openalex.org/W2156550631","https://openalex.org/W2155675690","https://openalex.org/W1563562883","https://openalex.org/W2185927297","https://openalex.org/W2111591643","https://openalex.org/W4245549415","https://openalex.org/W2163932442","https://openalex.org/W2030852227","https://openalex.org/W3151104204"],"abstract_inverted_index":{"Routability":[0],"is":[1],"a":[2,59,69,131],"mandatory":[3],"metric":[4],"for":[5],"modern":[6],"large-scale":[7],"mixed-size":[8,30],"circuit":[9],"placement":[10,66],"which":[11],"typically":[12],"needs":[13],"to":[14,97,111,123],"handle":[15],"hundreds":[16],"of":[17,22,44,101],"large":[18],"macros":[19,46],"and":[20,92,105,116,147,160],"millions":[21],"small":[23],"standard":[24,103],"cells.":[25],"However,":[26],"most":[27],"existing":[28],"academic":[29],"placers":[31],"either":[32],"focus":[33],"on":[34,47],"wirelength":[35],"minimization":[36],"alone,":[37],"or":[38],"do":[39],"not":[40],"consider":[41],"the":[42,88,93,99,135,157],"impact":[43],"movable":[45],"routing.":[48],"To":[49],"remedy":[50],"these":[51,138],"insufficiencies,":[52],"this":[53,81],"paper":[54,82],"formulates":[55],"design-hierarchy":[56,109],"information":[57,110],"as":[58],"novel":[60],"fence":[61,90],"force":[62,91],"in":[63],"an":[64],"analytical":[65],"framework.":[67],"Unlike":[68],"state-of-the-art":[70],"routability-driven":[71],"placer":[72,142,154],"that":[73,152],"simply":[74],"removes":[75],"net":[76],"bounding":[77],"boxes":[78],"during":[79],"placement,":[80],"utilizes":[83],"two":[84,139],"different":[85],"optimization":[86],"forces,":[87,140],"global":[89],"local":[94],"spreading":[95,121],"force,":[96],"determine":[98,112],"positions":[100],"both":[102],"cells":[104],"macros.":[106],"We":[107],"utilize":[108],"block":[113],"distributions":[114],"globally,":[115],"locally":[117],"we":[118],"add":[119],"additional":[120],"forces":[122],"preserve":[124],"sufficient":[125],"free":[126],"space":[127],"among":[128,163],"blocks":[129],"by":[130],"net-topology":[132],"estimation.":[133],"With":[134],"interactions":[136],"between":[137],"our":[141,153],"can":[143,155],"well":[144],"balance":[145],"routability":[146,159],"wirelength.":[148],"Experimental":[149],"results":[150],"show":[151],"achieve":[156],"best":[158],"routing":[161],"time":[162],"all":[164],"published":[165],"works.":[166]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-06T09:05:17.133730","created_date":"2025-10-10T00:00:00"}