{"id":"https://openalex.org/W4236108996","doi":"https://doi.org/10.1109/iccad.2010.5654154","title":"Mathematical yield estimation for two-dimensional-redundancy memory arrays","display_name":"Mathematical yield estimation for two-dimensional-redundancy memory arrays","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W4236108996","doi":"https://doi.org/10.1109/iccad.2010.5654154"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2010.5654154","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2010.5654154","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045156360","display_name":"Mango C.-T. Chao","orcid":"https://orcid.org/0000-0002-7299-9015"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mango C.-T. Chao","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075275148","display_name":"Ching-Yu Chin","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Yu Chin","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050123308","display_name":"Chen-Wei Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen-Wei Lin","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.1755,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.46551404,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"235","last_page":"240"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8862122893333435},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6833062171936035},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6717153787612915},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6352208852767944},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5304785370826721},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4470340311527252},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4257124960422516},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3872157335281372},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1750551164150238}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8862122893333435},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6833062171936035},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6717153787612915},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6352208852767944},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5304785370826721},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4470340311527252},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4257124960422516},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3872157335281372},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1750551164150238},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2010.5654154","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2010.5654154","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1722040935","https://openalex.org/W1792362277","https://openalex.org/W1922918362","https://openalex.org/W1988399408","https://openalex.org/W2124479423","https://openalex.org/W2128188365","https://openalex.org/W2134822007","https://openalex.org/W2136807836","https://openalex.org/W2138356008","https://openalex.org/W2146110695","https://openalex.org/W2148662885","https://openalex.org/W2155640457","https://openalex.org/W2156585715","https://openalex.org/W2169087039","https://openalex.org/W2169908140","https://openalex.org/W2171019527","https://openalex.org/W4234013965","https://openalex.org/W4256002266","https://openalex.org/W6678879412","https://openalex.org/W6680211006","https://openalex.org/W6680745762","https://openalex.org/W6683204303"],"related_works":["https://openalex.org/W2389214306","https://openalex.org/W4235240664","https://openalex.org/W2965083567","https://openalex.org/W1838576100","https://openalex.org/W2095886385","https://openalex.org/W2889616422","https://openalex.org/W2089704382","https://openalex.org/W1983399550","https://openalex.org/W97075385","https://openalex.org/W2133886031"],"abstract_inverted_index":{"Defect":[0],"repair":[1],"has":[2],"become":[3],"a":[4,16,45,52,62,81],"necessary":[5],"process":[6],"to":[7,37,65],"enhance":[8],"the":[9,39,67,91,97,109,112,120],"overall":[10],"yield":[11],"for":[12,125],"memories":[13],"since":[14],"manufacturing":[15],"natural":[17],"good":[18],"memory":[19,24,46,127],"is":[20],"difficult":[21],"in":[22,44],"current":[23],"technologies.":[25],"This":[26],"paper":[27],"presents":[28],"an":[29,34],"yield-estimation":[30,71,114],"scheme,":[31,115],"which":[32,59],"utilizes":[33],"induction-based":[35],"approach":[36],"calculate":[38],"probability":[40],"that":[41],"all":[42],"defects":[43,106],"can":[47,79,95,117],"be":[48],"successfully":[49],"repaired":[50],"by":[51,141],"two-dimensional":[53],"redundancy":[54,123],"design.":[55],"Unlike":[56],"previous":[57],"works,":[58],"rely":[60],"on":[61],"time-consuming":[63],"simulation":[64,144],"estimate":[66],"expected":[68],"yield,":[69],"our":[70],"scheme":[72,94],"only":[73],"requires":[74],"scalable":[75],"mathematical":[76],"computation":[77],"and":[78,87,104],"achieve":[80],"high":[82],"accuracy":[83],"with":[84],"limited":[85],"time":[86],"space":[88],"complexity.":[89],"Also,":[90],"proposed":[92,113],"estimation":[93],"consider":[96],"impact":[98],"of":[99,111],"single":[100],"defects,":[101,103],"column":[102],"row":[105],"simultaneously.":[107],"With":[108],"help":[110],"we":[116],"effectively":[118],"identify":[119],"most":[121],"profitable":[122],"configuration":[124],"large":[126],"designs":[128],"within":[129],"few":[130],"seconds":[131],"while":[132],"it":[133],"may":[134],"take":[135],"several":[136],"hours":[137],"or":[138],"even":[139],"days":[140],"using":[142],"conventional":[143],"approach.":[145]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}