{"id":"https://openalex.org/W4229745658","doi":"https://doi.org/10.1109/iccad.2008.4681608","title":"Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization","display_name":"Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W4229745658","doi":"https://doi.org/10.1109/iccad.2008.4681608"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2008.4681608","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2008.4681608","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/ACM International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082521899","display_name":"Yesin Ryu","orcid":null},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Yesin Ryu","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Seoul National University, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Seoul National University, South Korea","institution_ids":["https://openalex.org/I139264467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049474875","display_name":"Taewhan Kim","orcid":"https://orcid.org/0000-0002-6114-3772"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taewhan Kim","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Seoul National University, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Seoul National University, South Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5082521899"],"corresponding_institution_ids":["https://openalex.org/I139264467"],"apc_list":null,"apc_paid":null,"fwci":3.3294,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.92458923,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"416","last_page":"419"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.698956310749054},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5982654094696045},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5408412218093872},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5351899862289429},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5169247984886169},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5008296966552734},{"id":"https://openalex.org/keywords/ground-bounce","display_name":"Ground bounce","score":0.47739142179489136},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.47428470849990845},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.471037894487381},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.41951626539230347},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3238752782344818},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.25427672266960144},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2108561098575592},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.132224440574646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11151564121246338},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10488224029541016},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.09033951163291931},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08396682143211365}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.698956310749054},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5982654094696045},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5408412218093872},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5351899862289429},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5169247984886169},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5008296966552734},{"id":"https://openalex.org/C179053373","wikidata":"https://www.wikidata.org/wiki/Q1547690","display_name":"Ground bounce","level":5,"score":0.47739142179489136},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.47428470849990845},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.471037894487381},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.41951626539230347},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3238752782344818},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.25427672266960144},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2108561098575592},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.132224440574646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11151564121246338},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10488224029541016},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.09033951163291931},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08396682143211365},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C166972891","wikidata":"https://www.wikidata.org/wiki/Q5527011","display_name":"Gate dielectric","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2008.4681608","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2008.4681608","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/ACM International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.800000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337361","display_name":"National Institute of Environmental Health Sciences","ror":"https://ror.org/00j4k1h63"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1500653364","https://openalex.org/W1507707340","https://openalex.org/W2079770493","https://openalex.org/W2101929352","https://openalex.org/W2116259070","https://openalex.org/W2128237591","https://openalex.org/W2149417654","https://openalex.org/W2149613519","https://openalex.org/W4242862917","https://openalex.org/W6675992166"],"related_works":["https://openalex.org/W2174922170","https://openalex.org/W2133326759","https://openalex.org/W3006003651","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2040807843","https://openalex.org/W1564063853","https://openalex.org/W4230501858","https://openalex.org/W2559451387","https://openalex.org/W4249038728"],"abstract_inverted_index":{"A":[0],"new":[1],"approach":[2,138],"to":[3,77,104,114,167],"the":[4,16,25,44,59,67,79,92,96,106,123,148,154,160,171],"problem":[5,27],"of":[6,39,61,81,98,108,162],"clock":[7,17,36,45,68,117,124],"buffer":[8],"polarity":[9],"assignment":[10,26],"for":[11],"minimizing":[12,62],"power/ground":[13,63,99,109,149],"noise":[14,64,110,150],"on":[15,95],"network":[18],"is":[19,73,134,139],"presented.":[20],"The":[21],"previous":[22],"approaches":[23],"solve":[24],"in":[28],"two":[29],"separate":[30],"steps:":[31],"(step":[32,50],"1)":[33],"generating":[34],"a":[35,116],"routing":[37,118],"tree":[38,119],"minimum":[40],"total":[41],"wirelength,":[42],"satisfying":[43,66,122],"skew":[46,69,125],"constraint":[47],"and":[48,112,142,153],"then":[49,113],"2)":[51],"inserting":[52],"buffering":[53],"elements":[54],"with":[55],"their":[56],"polarities":[57],"under":[58],"objective":[60],"while":[65,121],"constraint.":[70,126],"Yet,":[71],"there":[72],"no":[74],"easy":[75],"way":[76],"predict":[78],"result":[80],"step":[82,85],"2":[83],"during":[84],"1.":[86],"In":[87],"our":[88],"approach,":[89],"we":[90,102],"place":[91],"primary":[93],"importance":[94],"cost":[97,107],"noise.":[100],"Consequently,":[101],"try":[103],"minimize":[105],"first":[111],"construct":[115],"later":[120],"Through":[127],"experimentation":[128],"using":[129],"several":[130],"benchmark":[131],"circuits,":[132],"it":[133],"shown":[135],"that":[136,168],"this":[137],"quite":[140],"effective":[141],"produces":[143],"very":[144],"good":[145],"solutions,":[146],"reducing":[147],"by":[151,157,170],"75%":[152],"peak":[155],"current":[156],"26%":[158],"at":[159],"expense":[161],"5%":[163],"wirelength":[164],"overhead":[165],"compared":[166],"produced":[169],"conventional":[172],"approach.":[173]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
