{"id":"https://openalex.org/W4256464978","doi":"https://doi.org/10.1109/iccad.2008.4681577","title":"Constraint graph-based macro placement for modern mixed-size circuit designs","display_name":"Constraint graph-based macro placement for modern mixed-size circuit designs","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W4256464978","doi":"https://doi.org/10.1109/iccad.2008.4681577"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2008.4681577","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2008.4681577","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/ACM International Conference on Computer-Aided Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009614985","display_name":"Hsin-Chen Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hsin-Chen Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075696706","display_name":"Yi-Lin Chuang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Lin Chuang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https://orcid.org/0000-0002-0564-5719"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","Genesys Logic, Inc., Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Genesys Logic, Inc., Taipei, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109071586","display_name":"Yung\u2010Chung Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Chung Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","Genesys Logic, Inc., Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Genesys Logic, Inc., Taipei, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5009614985"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.42402131,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"218","last_page":"223"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.9331346154212952},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7197796702384949},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6395164132118225},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5826371312141418},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5405551195144653},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.5178182721138},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.46767696738243103},{"id":"https://openalex.org/keywords/constraint-programming","display_name":"Constraint programming","score":0.4627198576927185},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33887404203414917},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3385275900363922},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.32872241735458374},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.21513652801513672},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15436604619026184},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.08769571781158447},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06749379634857178}],"concepts":[{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.9331346154212952},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7197796702384949},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6395164132118225},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5826371312141418},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5405551195144653},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.5178182721138},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.46767696738243103},{"id":"https://openalex.org/C173404611","wikidata":"https://www.wikidata.org/wiki/Q528588","display_name":"Constraint programming","level":3,"score":0.4627198576927185},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33887404203414917},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3385275900363922},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.32872241735458374},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.21513652801513672},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15436604619026184},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.08769571781158447},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06749379634857178},{"id":"https://openalex.org/C137631369","wikidata":"https://www.wikidata.org/wiki/Q7617831","display_name":"Stochastic programming","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2008.4681577","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2008.4681577","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/ACM International Conference on Computer-Aided Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1969091636","https://openalex.org/W2002525234","https://openalex.org/W2010879706","https://openalex.org/W2022749924","https://openalex.org/W2024392966","https://openalex.org/W2064592593","https://openalex.org/W2090243586","https://openalex.org/W2103833707","https://openalex.org/W2114796612","https://openalex.org/W2147899388","https://openalex.org/W2153770483","https://openalex.org/W2167190617","https://openalex.org/W3140686304","https://openalex.org/W4237299108","https://openalex.org/W4241644863","https://openalex.org/W4252814110","https://openalex.org/W6661909638"],"related_works":["https://openalex.org/W1969091636","https://openalex.org/W4388820510","https://openalex.org/W4239988924","https://openalex.org/W2774125915","https://openalex.org/W2055907840","https://openalex.org/W4255072499","https://openalex.org/W2058407220","https://openalex.org/W2997784719","https://openalex.org/W4256464978","https://openalex.org/W2293911681"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"a":[5,70],"constraint":[6,27],"graph-based":[7],"macro":[8,13,17,48,72,92,112],"placement":[9,49,73,78,85],"algorithm":[10,43,95],"that":[11,110],"removes":[12],"overlaps":[14],"and":[15,52,77,82,98,116],"optimizes":[16],"positions":[18],"for":[19,46,103],"modern":[20],"mixed-size":[21],"circuit":[22],"designs.":[23],"Improving":[24],"over":[25],"the":[26,39,101],"graph":[28],"by":[29,74],"working":[30],"only":[31],"on":[32],"its":[33],"essential":[34],"edges":[35],"without":[36],"loss":[37],"of":[38,55],"solution":[40],"quality,":[41],"our":[42,66,94,111],"can":[44,68,96],"search":[45],"high-quality":[47],"solutions":[50],"effectively":[51],"efficiently.":[53],"Instead":[54],"packing":[56],"macros":[57],"along":[58],"chip":[59],"boundaries":[60],"like":[61],"most":[62],"recent":[63],"previous":[64],"work,":[65],"placer":[67,113],"determine":[69],"non-compacted":[71],"linear":[75],"programming":[76],"region":[79],"cost":[80],"evaluation":[81],"handle":[83],"various":[84,89],"constraints/objectives.":[86],"Compared":[87],"with":[88,105],"leading":[90],"academic":[91],"placers,":[93],"consistently":[97],"significantly":[99],"reduce":[100],"wirelengths":[102],"designs":[104],"different":[106],"utilization":[107],"rates,":[108],"implying":[109],"is":[114],"robust":[115],"has":[117],"very":[118],"high":[119],"quality.":[120]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}