{"id":"https://openalex.org/W4246911015","doi":"https://doi.org/10.1109/iccad.2005.1560102","title":"Noise margin analysis for dynamic logic circuits","display_name":"Noise margin analysis for dynamic logic circuits","publication_year":2005,"publication_date":"2005-12-22","ids":{"openalex":"https://openalex.org/W4246911015","doi":"https://doi.org/10.1109/iccad.2005.1560102"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2005.1560102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2005.1560102","pdf_url":null,"source":{"id":"https://openalex.org/S4363608058","display_name":"ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Suwen Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Suwen Yang","raw_affiliation_strings":["Department of Computer Science, University of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042293731","display_name":"M. Greenstreet","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Greenstreet","raw_affiliation_strings":["Department of Computer Science, University of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":0.5448,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.70833877,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"406","last_page":"412"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11206","display_name":"Model Reduction and Neural Networks","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.7674911022186279},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.686615526676178},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6081048250198364},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5782337188720703},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5461848378181458},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5429271459579468},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5179137587547302},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4735666513442993},{"id":"https://openalex.org/keywords/noise-immunity","display_name":"Noise immunity","score":0.47103410959243774},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.44778215885162354},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3613121509552002},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.3454267382621765},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3227846622467041},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21658772230148315},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1321220099925995},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.12551680207252502},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10183027386665344},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09357073903083801},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09228631854057312}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.7674911022186279},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.686615526676178},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6081048250198364},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5782337188720703},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5461848378181458},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5429271459579468},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5179137587547302},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4735666513442993},{"id":"https://openalex.org/C2988494973","wikidata":"https://www.wikidata.org/wiki/Q179448","display_name":"Noise immunity","level":3,"score":0.47103410959243774},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.44778215885162354},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3613121509552002},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.3454267382621765},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3227846622467041},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21658772230148315},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1321220099925995},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.12551680207252502},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10183027386665344},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09357073903083801},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09228631854057312},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2005.1560102","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2005.1560102","pdf_url":null,"source":{"id":"https://openalex.org/S4363608058","display_name":"ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1536153721","https://openalex.org/W2064169027","https://openalex.org/W2104869059","https://openalex.org/W2121866048","https://openalex.org/W2164116828","https://openalex.org/W4233559368","https://openalex.org/W4238696474"],"related_works":["https://openalex.org/W1513486344","https://openalex.org/W2082788688","https://openalex.org/W1996043106","https://openalex.org/W3201227081","https://openalex.org/W2014775954","https://openalex.org/W1634085391","https://openalex.org/W2529167390","https://openalex.org/W1668918857","https://openalex.org/W2488971671","https://openalex.org/W2045506892"],"abstract_inverted_index":{"We":[0,26,55,78],"consider":[1],"the":[2,39,50,53,72,76,84],"problem":[3,35],"of":[4,52,75,86],"noise":[5,20,28],"margin":[6,29],"analysis":[7,30],"for":[8,60,71],"dynamic":[9],"logic":[10],"circuits.":[11],"Because":[12],"such":[13],"circuits":[14],"operate":[15],"in":[16,45,49],"multiple":[17],"phases,":[18],"their":[19],"immunity":[21],"is":[22],"also":[23],"time":[24],"varying.":[25],"formulate":[27],"as":[31],"a":[32,46,57,68],"non-linear":[33],"optimization":[34,63],"where":[36],"we":[37],"find":[38],"smallest":[40],"disturbance":[41],"waveform":[42],"that":[43],"results":[44],"qualitative":[47],"change":[48],"behavior":[51],"circuit.":[54,77],"present":[56],"practical":[58],"method":[59],"solving":[61],"these":[62],"problems":[64],"based":[65],"on":[66],"deriving":[67],"sensitivity":[69],"matrix":[70],"small-signal":[73],"response":[74],"use":[79],"our":[80],"approach":[81],"to":[82],"compare":[83],"robustness":[85],"static":[87],"CMOS":[88],"gates,":[89],"self-resetting":[90],"domino,":[91],"and":[92],"output":[93],"prediction":[94],"logic.":[95]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2015,"cited_by_count":3}],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-10-10T00:00:00"}