{"id":"https://openalex.org/W4241627104","doi":"https://doi.org/10.1109/iccad.2005.1560061","title":"Synthesis methodology for built-in at-speed testing","display_name":"Synthesis methodology for built-in at-speed testing","publication_year":2005,"publication_date":"2005-12-22","ids":{"openalex":"https://openalex.org/W4241627104","doi":"https://doi.org/10.1109/iccad.2005.1560061"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2005.1560061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2005.1560061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100413684","display_name":"Yinghua Li","orcid":"https://orcid.org/0000-0003-1390-0393"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yinghua Li","raw_affiliation_strings":["Cadence Berkeley Laboratories, University of California Berkeley, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Berkeley Laboratories, University of California Berkeley, USA","institution_ids":["https://openalex.org/I148283060","https://openalex.org/I66217453","https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051382573","display_name":"A. Kondratyev","orcid":null},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Kondratyev","raw_affiliation_strings":["Cadence Berkeley Laboratories, University of California Berkeley, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Berkeley Laboratories, University of California Berkeley, USA","institution_ids":["https://openalex.org/I148283060","https://openalex.org/I66217453","https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028784624","display_name":"R. Brayton","orcid":null},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Brayton","raw_affiliation_strings":["Cadence Berkeley Laboratories, University of California Berkeley, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Berkeley Laboratories, University of California Berkeley, USA","institution_ids":["https://openalex.org/I148283060","https://openalex.org/I66217453","https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"183","last_page":"188"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7656720876693726},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.7411534786224365},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5683938264846802},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5624806880950928},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4874577522277832},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40821295976638794},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33483409881591797},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33026719093322754},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3116663992404938},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11152154207229614},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09120309352874756}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7656720876693726},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.7411534786224365},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5683938264846802},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5624806880950928},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4874577522277832},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40821295976638794},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33483409881591797},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33026719093322754},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3116663992404938},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11152154207229614},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09120309352874756}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2005.1560061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2005.1560061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1484446818","https://openalex.org/W1984588379","https://openalex.org/W2052652173","https://openalex.org/W2100322482","https://openalex.org/W2120566121","https://openalex.org/W2157100834","https://openalex.org/W2476901852","https://openalex.org/W4231905827","https://openalex.org/W4236432903","https://openalex.org/W4254506919","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W2144453115","https://openalex.org/W2128223750","https://openalex.org/W4238532390","https://openalex.org/W2188872161","https://openalex.org/W2961779879","https://openalex.org/W797688974","https://openalex.org/W2002978035","https://openalex.org/W2209382646"],"abstract_inverted_index":{"We":[0,58],"discuss":[1],"a":[2,46,60],"new":[3],"synthesis":[4],"flow,":[5],"which":[6,49,98],"offers":[7],"the":[8,85,96],"ability":[9],"to":[10,27,44,52,95],"do":[11],"easy":[12],"delay":[13],"testing":[14,62],"almost":[15],"free":[16],"in":[17,38],"terms":[18],"of":[19,84],"its":[20],"impact":[21],"on":[22,54],"speed":[23],"and":[24,41,102],"area":[25],"compared":[26],"corresponding":[28,78],"implementations":[29],"with":[30],"standard":[31],"cells.":[32],"The":[33,81],"methodology":[34],"uses":[35],"matched":[36,66,86],"delays":[37,67,87],"pre-charged":[39],"PLAs":[40],"bundled":[42],"routing":[43],"produce":[45],"completion":[47,73],"signal,":[48],"is":[50],"guaranteed":[51],"lie":[53],"all":[55,72],"critical":[56],"paths.":[57],"give":[59],"nondelay":[61],"method":[63],"for":[64],"ensuring":[65],"are":[68,93,99],"correct,":[69],"i.e.":[70],"that":[71],"signals":[74],"arrive":[75],"after":[76],"their":[77],"data":[79],"signals.":[80],"design":[82],"margins":[83],"can":[88],"be":[89],"small":[90],"since":[91],"they":[92],"internal":[94],"PLAs,":[97],"regular":[100],"structures":[101],"therefore":[103],"more":[104],"predictable.":[105]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2025-10-10T00:00:00"}
