{"id":"https://openalex.org/W1566076317","doi":"https://doi.org/10.1109/iccad.2004.1382702","title":"Minimizing the number of test configurations for FPGAs","display_name":"Minimizing the number of test configurations for FPGAs","publication_year":2005,"publication_date":"2005-02-22","ids":{"openalex":"https://openalex.org/W1566076317","doi":"https://doi.org/10.1109/iccad.2004.1382702","mag":"1566076317"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2004.1382702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382702","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034183191","display_name":"Erik Chmelar","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"E. Chmelar","raw_affiliation_strings":["Center for Reliable Computing, University of Stanford, USA","Center for Reliable Comput., Stanford Univ., Palo Alto, CA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Reliable Computing, University of Stanford, USA","institution_ids":[]},{"raw_affiliation_string":"Center for Reliable Comput., Stanford Univ., Palo Alto, CA, USA#TAB#","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5034183191"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.07265494,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"899","last_page":"902"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8572232127189636},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.8546854257583618},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6575163006782532},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6483117341995239},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5923891067504883},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.49776509404182434},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4873426854610443},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47436055541038513},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.39520007371902466},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36037033796310425},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09910774230957031},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08403611183166504}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8572232127189636},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.8546854257583618},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6575163006782532},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6483117341995239},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5923891067504883},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.49776509404182434},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4873426854610443},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47436055541038513},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.39520007371902466},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36037033796310425},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09910774230957031},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08403611183166504}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2004.1382702","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382702","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1519752471","https://openalex.org/W1573539205","https://openalex.org/W1889269054","https://openalex.org/W1916533169","https://openalex.org/W2116732528","https://openalex.org/W2153639215","https://openalex.org/W2160009688","https://openalex.org/W2165446236","https://openalex.org/W2168253620","https://openalex.org/W6684616284"],"related_works":["https://openalex.org/W2039899645","https://openalex.org/W2258948885","https://openalex.org/W2371342700","https://openalex.org/W2544043553","https://openalex.org/W2327110311","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2363059241","https://openalex.org/W3215187042","https://openalex.org/W2540393334"],"abstract_inverted_index":{"FPGA":[0],"test":[1,12,15,52],"cost":[2],"can":[3],"be":[4],"greatly":[5],"reduced":[6],"by":[7],"minimizing":[8],"the":[9],"number":[10],"of":[11,36],"configurations.":[13],"A":[14],"technique":[16],"is":[17,33,41],"presented":[18],"for":[19,44],"FPGAs":[20,49],"with":[21],"multiplexer-based":[22],"routing":[23],"architectures":[24],"in":[25],"which":[26],"multiple":[27],"logical":[28],"paths":[29],"through":[30],"each":[31],"multiplexer":[32],"enabled":[34],"instead":[35],"only":[37,50],"one":[38],"path.":[39],"It":[40],"shown":[42],"that":[43],"Xilinx":[45],"Virtex-II":[46],"and":[47,62],"Spartan-3":[48],"8":[51],"configurations":[53],"are":[54],"required":[55],"to":[56],"achieve":[57],"100%":[58],"stuck-at,":[59],"PIP":[60,63],"stuck-on,":[61],"stuck-off":[64],"fault":[65],"coverage.":[66]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}