{"id":"https://openalex.org/W1556439630","doi":"https://doi.org/10.1109/iccad.2004.1382676","title":"Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth","display_name":"Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth","publication_year":2005,"publication_date":"2005-02-22","ids":{"openalex":"https://openalex.org/W1556439630","doi":"https://doi.org/10.1109/iccad.2004.1382676","mag":"1556439630"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2004.1382676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058899830","display_name":"Maxim Teslenko","orcid":null},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"M. Teslenko","raw_affiliation_strings":["IMIT, KTH, Royal Institute of Technology, Kista, Sweden","IMIT/KTH, Royal Institute of Technology, Kista, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMIT, KTH, Royal Institute of Technology, Kista, Sweden","institution_ids":["https://openalex.org/I86987016"]},{"raw_affiliation_string":"IMIT/KTH, Royal Institute of Technology, Kista, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011438358","display_name":"Elena Dubrova","orcid":"https://orcid.org/0000-0001-7382-9408"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"E. Dubrova","raw_affiliation_strings":["IMIT/KTH, Royal Institute of Technology, Kista, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMIT/KTH, Royal Institute of Technology, Kista, Sweden","institution_ids":["https://openalex.org/I86987016"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I86987016"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"748","last_page":"751"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.9556339979171753},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7709006071090698},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7148263454437256},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5897680521011353},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.5161401033401489},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5137775540351868},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48063674569129944},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27419018745422363}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.9556339979171753},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7709006071090698},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7148263454437256},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5897680521011353},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.5161401033401489},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5137775540351868},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48063674569129944},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27419018745422363},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2004.1382676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1806428288","https://openalex.org/W1976357819","https://openalex.org/W1978998136","https://openalex.org/W1985457698","https://openalex.org/W2021513464","https://openalex.org/W2021709993","https://openalex.org/W2026761397","https://openalex.org/W2030094243","https://openalex.org/W2099788146","https://openalex.org/W2104232897","https://openalex.org/W2105355057","https://openalex.org/W2105715355","https://openalex.org/W2108914609","https://openalex.org/W2112557094","https://openalex.org/W2116677904","https://openalex.org/W2137806747","https://openalex.org/W2150787480","https://openalex.org/W2167328871","https://openalex.org/W2171775842","https://openalex.org/W4213060883","https://openalex.org/W4237405987","https://openalex.org/W4242059762","https://openalex.org/W4252217915","https://openalex.org/W6675301554","https://openalex.org/W6834495128"],"related_works":["https://openalex.org/W2798215405","https://openalex.org/W2990962948","https://openalex.org/W2111241003","https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2131696304","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W2160958666"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"Hermes,":[3],"a":[4,17,26,30,52],"depth-optimal":[5],"LUT":[6,28,47,76],"based":[7,15],"FPGA":[8],"mapping":[9],"algorithm.":[10],"The":[11,39,61,96],"presented":[12,69],"algorithm":[13,70],"is":[14,43],"on":[16,66],"new":[18],"strategy":[19],"for":[20,103],"finding":[21],"LUTs":[22],"allowing":[23],"to":[24,35,79],"find":[25],"good":[27],"in":[29,105],"significantly":[31],"shorter":[32],"time":[33],"compared":[34,78],"the":[36,68,80],"previous":[37],"methods.":[38],"quality":[40],"of":[41,91,98],"results":[42,63],"improved":[44],"by":[45,50,83],"enabling":[46],"re-implementation":[48],"and":[49,73,85],"introducing":[51],"cost":[53],"function":[54],"which":[55],"encourages":[56],"input":[57],"sharing":[58],"among":[59],"LUTs.":[60],"experimental":[62],"show":[64],"that,":[65],"average,":[67],"computes":[71],"15.5%":[72],"3.5%":[74],"smaller":[75],"mappings":[77],"ones":[81],"obtained":[82],"FlowMap":[84],"CutMap,":[86],"respectively,":[87],"using":[88],"two":[89],"orders":[90],"magnitude":[92],"less":[93],"CPU":[94],"time.":[95],"speed":[97],"Hermes":[99],"makes":[100],"it":[101],"suitable":[102],"running":[104],"an":[106],"incremental":[107],"manner":[108],"during":[109],"logic":[110],"synthesis.":[111]},"counts_by_year":[{"year":2020,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
