{"id":"https://openalex.org/W1525696892","doi":"https://doi.org/10.1109/iccad.2004.1382639","title":"Unification of partitioning, placement and floorplanning","display_name":"Unification of partitioning, placement and floorplanning","publication_year":2005,"publication_date":"2005-02-22","ids":{"openalex":"https://openalex.org/W1525696892","doi":"https://doi.org/10.1109/iccad.2004.1382639","mag":"1525696892"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2004.1382639","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382639","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068392026","display_name":"Saurabh Adya","orcid":"https://orcid.org/0009-0000-4533-6577"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"S.N. Adya","raw_affiliation_strings":["Synplicity, Inc., Sunnyvale, CA, USA"],"affiliations":[{"raw_affiliation_string":"Synplicity, Inc., Sunnyvale, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068867173","display_name":"Shashank Chaturvedi","orcid":"https://orcid.org/0000-0001-9151-694X"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]},{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]}],"countries":["CA","US"],"is_corresponding":false,"raw_author_name":"S. Chaturvedi","raw_affiliation_strings":["Advanced Micro Devices, Inc., Austin, TX, USA","Adv. Micro Devices, Austin, TX"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Inc., Austin, TX, USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"Adv. Micro Devices, Austin, TX","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110108098","display_name":"Jarrod A. Roy","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Roy","raw_affiliation_strings":["EECS Department, University of Michigan, Ann Arbor, MI, USA","University of Michigan, EECS Department, Ann Arbor, MI#TAB#"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan, EECS Department, Ann Arbor, MI#TAB#","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067863557","display_name":"David Papa","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.A. Papa","raw_affiliation_strings":["EECS Department, University of Michigan, Ann Arbor, MI, USA","University of Michigan, EECS Department, Ann Arbor, MI#TAB#"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan, EECS Department, Ann Arbor, MI#TAB#","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065370018","display_name":"Igor L. Markov","orcid":"https://orcid.org/0000-0002-3826-527X"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan\u2013Ann Arbor","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"I.L. Markov","raw_affiliation_strings":["EECS Department, University of Michigan, Ann Arbor, MI, USA","University of Michigan, EECS Department, Ann Arbor, MI#TAB#"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan, EECS Department, Ann Arbor, MI#TAB#","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5068392026"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":31.1971,"has_fulltext":false,"cited_by_count":170,"citation_normalized_percentile":{"value":0.9985711,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"550","last_page":"557"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9879223108291626},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.678589940071106},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6757269501686096},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6048632860183716},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6033620834350586},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5627878904342651},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5173965692520142},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.510001540184021},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5061003565788269},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.42824625968933105},{"id":"https://openalex.org/keywords/undo","display_name":"Undo","score":0.4148308038711548},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3288625478744507},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32181063294410706},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2568560242652893},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2439272701740265},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22971203923225403}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9879223108291626},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.678589940071106},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6757269501686096},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6048632860183716},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6033620834350586},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5627878904342651},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5173965692520142},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.510001540184021},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5061003565788269},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.42824625968933105},{"id":"https://openalex.org/C2780154230","wikidata":"https://www.wikidata.org/wiki/Q513420","display_name":"Undo","level":2,"score":0.4148308038711548},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3288625478744507},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32181063294410706},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2568560242652893},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2439272701740265},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22971203923225403},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2004.1382639","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382639","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6000000238418579,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1966730830","https://openalex.org/W1976292780","https://openalex.org/W1981341140","https://openalex.org/W1982113699","https://openalex.org/W1983250183","https://openalex.org/W2003764518","https://openalex.org/W2024392966","https://openalex.org/W2047144269","https://openalex.org/W2048508570","https://openalex.org/W2048796234","https://openalex.org/W2075265327","https://openalex.org/W2095550547","https://openalex.org/W2098851424","https://openalex.org/W2102502584","https://openalex.org/W2107668615","https://openalex.org/W2114772983","https://openalex.org/W2115762048","https://openalex.org/W2120970098","https://openalex.org/W2126058624","https://openalex.org/W2127878666","https://openalex.org/W2142356348","https://openalex.org/W2150369487","https://openalex.org/W2152701040","https://openalex.org/W2156954556","https://openalex.org/W2160408075","https://openalex.org/W2165112989","https://openalex.org/W2167841124","https://openalex.org/W2167848093","https://openalex.org/W2172326478","https://openalex.org/W3141674929","https://openalex.org/W4205582583","https://openalex.org/W4237664122","https://openalex.org/W4241644863","https://openalex.org/W4242608849","https://openalex.org/W4245011336","https://openalex.org/W4245781162"],"related_works":["https://openalex.org/W2903073708","https://openalex.org/W2115502122","https://openalex.org/W2001838379","https://openalex.org/W4211105560","https://openalex.org/W2138401961","https://openalex.org/W1525696892","https://openalex.org/W2353155791","https://openalex.org/W2156550631","https://openalex.org/W1974073956","https://openalex.org/W2152053859"],"abstract_inverted_index":{"Large":[0,43],"macro":[1],"blocks,":[2],"pre-designed":[3],"datapaths,":[4],"embedded":[5,172],"memories":[6,173],"and":[7,33,59,106,137,156,174],"analog":[8],"blocks":[9],"are":[10,40,52],"increasingly":[11],"used":[12,187],"in":[13,30,57,78],"ASIC":[14],"designs.":[15],"However,":[16],"robust":[17],"algorithms":[18],"for":[19,56,147,160,176],"large-scale":[20],"placement":[21,88,97,105,135,146],"of":[22,75,80,112,158],"such":[23],"designs":[24,170],"have":[25],"only":[26],"recently":[27],"been":[28,166],"considered":[29],"the":[31,63,94,124,139,148,154],"literature,":[32],"improvements":[34],"by":[35,48],"over":[36],"10%":[37],"per":[38],"paper":[39],"still":[41],"common.":[42],"macros":[44],"can":[45,185],"be":[46,186],"handled":[47],"traditional":[49,66,161],"floorplanning,":[50,103],"but":[51],"harder":[53],"to":[54,72,85,92,142],"account":[55],"min-cut":[58,87,113],"analytical":[60],"placement.":[61],"On":[62],"other":[64],"hand,":[65],"floorplanning":[67,120,184],"techniques":[68],"do":[69],"not":[70],"scale":[71],"large":[73],"numbers":[74],"objects,":[76],"especially":[77],"terms":[79],"solution":[81],"quality.":[82],"We":[83],"propose":[84,180],"integrate":[86],"with":[89,171,188],"fixed-outline":[90,119],"floor-planning":[91],"solve":[93],"more":[95],"general":[96],"problem,":[98],"which":[99],"includes":[100],"cell":[101],"placement,":[102,114],"mixed-size":[104],"achieving":[107],"routability.":[108,177],"At":[109],"every":[110],"step":[111],"either":[115],"partitioning":[116,131],"or":[117],"wirelength-driven,":[118],"is":[121],"invoked.":[122],"If":[123],"latter":[125],"fails,":[126],"we":[127,179],"undo":[128],"an":[129],"earlier":[130],"decision,":[132],"merge":[133],"adjacent":[134],"regions":[136],"re-floorplan":[138],"larger":[140],"region":[141],"find":[143],"a":[144],"legal":[145],"macros.":[149],"Empirically,":[150],"this":[151],"framework":[152],"improves":[153],"scalability":[155],"quality":[157],"results":[159],"wirelength-driven":[162],"floorplanning.":[163],"It":[164],"has":[165],"validated":[167],"on":[168],"recent":[169],"accounts":[175],"Additionally,":[178],"that":[181],"free-shape":[182],"rectilinear":[183],"rough":[189],"module-area":[190],"estimates":[191],"before":[192],"synthesis.":[193]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":6}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}