{"id":"https://openalex.org/W1573997715","doi":"https://doi.org/10.1109/iccad.2004.1382613","title":"M-trie: an efficient approach to on-chip logic minimization","display_name":"M-trie: an efficient approach to on-chip logic minimization","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W1573997715","doi":"https://doi.org/10.1109/iccad.2004.1382613","mag":"1573997715"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2004.1382613","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382613","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030075847","display_name":"S. Ahmand","orcid":null},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Ahmand","raw_affiliation_strings":["Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076611650","display_name":"Rajarshi Mahapatra","orcid":"https://orcid.org/0000-0003-0155-0218"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Mahapatra","raw_affiliation_strings":["Department of Computer Science, Texas A & M University, College Station, Texas, USA","Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Texas A & M University, College Station, Texas, USA","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Texas A & M Univ., College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0561,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.77614093,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"428","last_page":"435"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9803000092506409,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9764000177383423,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.734841525554657},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6948401927947998},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6410109996795654},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5229114890098572},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5216732025146484},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.48128432035446167},{"id":"https://openalex.org/keywords/trie","display_name":"Trie","score":0.47317272424697876},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43198055028915405},{"id":"https://openalex.org/keywords/data-structure","display_name":"Data structure","score":0.2552698850631714}],"concepts":[{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.734841525554657},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6948401927947998},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6410109996795654},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5229114890098572},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5216732025146484},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.48128432035446167},{"id":"https://openalex.org/C190290938","wikidata":"https://www.wikidata.org/wiki/Q387015","display_name":"Trie","level":3,"score":0.47317272424697876},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43198055028915405},{"id":"https://openalex.org/C162319229","wikidata":"https://www.wikidata.org/wiki/Q175263","display_name":"Data structure","level":2,"score":0.2552698850631714},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.2004.1382613","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2004.1382613","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W146811354","https://openalex.org/W2028265666","https://openalex.org/W2105761964","https://openalex.org/W2137216984","https://openalex.org/W2137231558","https://openalex.org/W2140156318","https://openalex.org/W2151970267","https://openalex.org/W2171069885","https://openalex.org/W4206627859"],"related_works":["https://openalex.org/W1553855433","https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2170504327","https://openalex.org/W2789349722","https://openalex.org/W2766377030","https://openalex.org/W1987454796","https://openalex.org/W2102927888"],"abstract_inverted_index":{"Boolean":[0],"logic":[1,31,39,54,103],"minimization":[2,16,40,104],"is":[3,64,82],"being":[4],"increasingly":[5],"applied":[6],"to":[7,66,91],"new":[8,37],"applications":[9,19],"which":[10],"demands":[11],"very":[12,22],"fast":[13],"and":[14,25,52,60,70],"frequent":[15],"services.":[17],"These":[18],"typically":[20],"offer":[21],"limited":[23],"computing":[24],"memory":[26,76],"resources":[27],"rendering":[28],"the":[29],"traditional":[30],"minimizers":[32,55],"ineffective.":[33],"We":[34,46],"present":[35],"a":[36,74],"approximate":[38],"algorithm":[41],"based":[42],"on":[43],"ternary":[44],"trie.":[45],"compare":[47],"its":[48],"performance":[49],"with":[50,73],"Espresso-II":[51],"ROCM":[53],"for":[56],"routing":[57],"table":[58],"compaction":[59],"demonstrate":[61],"that":[62,85],"it":[63],"100":[65],"1000":[67],"times":[68],"faster":[69],"can":[71,88],"run":[72],"data":[75],"as":[77,79,99],"little":[78],"16KB.":[80],"It":[81],"also":[83],"found":[84],"proposed":[86],"approach":[87],"support":[89],"up":[90],"25000":[92],"incremental":[93],"updates":[94],"per":[95],"seconds":[96],"positioning":[97],"itself":[98],"an":[100],"ideal":[101],"on-chip":[102],"algorithm.":[105]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
