{"id":"https://openalex.org/W1569461127","doi":"https://doi.org/10.1109/iccad.2004.1382587","title":"Exploiting level sensitive latches in wire pipelining","display_name":"Exploiting level sensitive latches in wire pipelining","publication_year":2005,"publication_date":"2005-02-22","ids":{"openalex":"https://openalex.org/W1569461127","doi":"https://doi.org/10.1109/iccad.2004.1382587","mag":"1569461127"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2004.1382587","is_oa":false,"landing_page_url":"http://doi.org/10.1109/iccad.2004.1382587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037347509","display_name":"V. Seth","orcid":null},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"V. Seth","raw_affiliation_strings":["Dept. of Electr Eng., Texas A&M Univ., College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electr Eng., Texas A&M Univ., College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101784756","display_name":"Min Zhao","orcid":"https://orcid.org/0000-0003-0553-5146"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Min Zhao","raw_affiliation_strings":["Tabula Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Tabula Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Dept of ECE, Northwestern Univ., Evanston, IL, USA"],"affiliations":[{"raw_affiliation_string":"Dept of ECE, Northwestern Univ., Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037347509"],"corresponding_institution_ids":["https://openalex.org/I91045830"],"apc_list":null,"apc_paid":null,"fwci":2.5393,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.88710297,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"283","last_page":"290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8110877275466919},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6932584047317505},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.532914400100708},{"id":"https://openalex.org/keywords/steiner-tree-problem","display_name":"Steiner tree problem","score":0.5003890991210938},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.42812085151672363},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35116589069366455},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.2901129722595215},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22684252262115479},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.20913711190223694},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12474921345710754}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8110877275466919},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6932584047317505},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.532914400100708},{"id":"https://openalex.org/C76220878","wikidata":"https://www.wikidata.org/wiki/Q1764144","display_name":"Steiner tree problem","level":2,"score":0.5003890991210938},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.42812085151672363},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35116589069366455},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2901129722595215},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22684252262115479},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20913711190223694},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12474921345710754},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iccad.2004.1382587","is_oa":false,"landing_page_url":"http://doi.org/10.1109/iccad.2004.1382587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.112.8357","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.112.8357","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.iccad.com/data2/iccad/iccad_04acceptedpapers.nsf/9cfb1ebaaf59043587256a6a00031f78/a2ef63d5821e55a087256ebb005d00ff/$file/04b03.pdf","raw_type":"text"},{"id":"pmh:oai:oaktrust.library.tamu.edu:1969.1/1433","is_oa":false,"landing_page_url":"https://hdl.handle.net/1969.1/1433","pdf_url":null,"source":{"id":"https://openalex.org/S4306400291","display_name":"OakTrust (Texas A&M University Libraries)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I91045830","host_organization_name":"Texas A&M University","host_organization_lineage":["https://openalex.org/I91045830"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Book"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2109059344","https://openalex.org/W2119211217","https://openalex.org/W2122769715","https://openalex.org/W2123316553","https://openalex.org/W2129943737","https://openalex.org/W2156162117","https://openalex.org/W2160252016","https://openalex.org/W2160521563","https://openalex.org/W2165089524","https://openalex.org/W2169049905","https://openalex.org/W2180470884","https://openalex.org/W4236324780","https://openalex.org/W6676367018"],"related_works":["https://openalex.org/W2118320476","https://openalex.org/W2161182859","https://openalex.org/W2025658531","https://openalex.org/W1503036335","https://openalex.org/W4244816249","https://openalex.org/W2115973883","https://openalex.org/W2739242419","https://openalex.org/W1585318792","https://openalex.org/W59641357","https://openalex.org/W28092394"],"abstract_inverted_index":{"The":[0,14,47,68,97,149,166],"present":[1],"research":[2],"presents":[3],"procedures":[4,134],"for":[5,105,120,179],"exploitation":[6],"of":[7,26,44,53,124,141],"level":[8],"sensitive":[9],"latches":[10,180],"in":[11,33,78,161],"wire":[12],"pipelining.":[13,148],"user":[15,48],"gives":[16],"a":[17,21,51,79,162],"Steiner":[18,126],"tree,":[19,127],"having":[20],"signal":[22],"source":[23,93],"and":[24,30,38,57,61,74,94,112,116,138],"set":[25],"destination":[27],"or":[28],"sinks,":[29],"the":[31,45,84,92,95,114,125,136,157,175],"location":[32],"rectangular":[34],"plane,":[35],"capacitive":[36],"load":[37],"required":[39],"arrival":[40],"time":[41],"at":[42],"each":[43,106],"destinations.":[46,96],"also":[49,63],"defines":[50],"library":[52],"non-clocked":[54],"(buffer)":[55],"elements":[56,59],"clocked":[58],"(flip-flop":[60],"latch),":[62],"known":[64],"as":[65],"synchronous":[66,75,117],"elements.":[67],"first":[69],"procedure":[70,99,151],"performs":[71],"concurrent":[72],"repeater":[73,115],"element":[76,118],"insertion":[77],"bottom-up":[80],"manner":[81],"to":[82,155],"find":[83],"minimum":[85],"latency":[86,137],"that":[87,159],"may":[88],"be":[89],"achieved":[90],"between":[91],"second":[98,150],"takes":[100],"additional":[101],"input":[102],"(required":[103],"latency)":[104],"destination,":[107],"derived":[108],"from":[109],"previous":[110],"procedure,":[111],"finds":[113],"assignments":[119],"all":[121],"internal":[122],"nodes":[123],"which":[128,173],"minimize":[129],"overall":[130],"area":[131,139],"used.":[132],"These":[133],"utilize":[135],"advantages":[140],"latch":[142,163],"based":[143,147,164],"pipelining":[144],"over":[145],"flip-flop":[146],"suggests":[152],"two":[153],"methods":[154],"tackle":[156],"challenges":[158],"exist":[160],"design.":[165],"deferred":[167],"delay":[168],"padding":[169],"technique":[170],"is":[171],"introduced,":[172],"removes":[174],"short":[176],"path":[177],"violations":[178],"with":[181],"minimal":[182],"extra":[183],"cost.":[184]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
